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blocco a spirale
- Joined Jun 18, 2008
- 1,546
Apart from the 'touch' plate feature (although this could be incorporated) this circuit should provide the function the TS requires and with a low
component count.
This is essentially an SR flip-flop with a slight modification so that both 00 and 11 are valid inputs. This means that if the latch is being set it cannot
be reset but all other latches connected to the reset line (those that are not being set) will be cleared. i.e. every time a new relay is latched all others
will be cleared to provide the exclusive function.
The reset pulse is derived from the NOT Q output which pulses the reset line (via transistor Q1) to clear all other latches whenever the Q output is set.
Components R3, Q1 and R2 form the common reset circuit and, therefore, should not be be repeated. Additional latches connect into the reset circuit
at the points marked with the red dots.
A single CMOS 4011 Quad NAND gate IC handles the logic.
component count.
This is essentially an SR flip-flop with a slight modification so that both 00 and 11 are valid inputs. This means that if the latch is being set it cannot
be reset but all other latches connected to the reset line (those that are not being set) will be cleared. i.e. every time a new relay is latched all others
will be cleared to provide the exclusive function.
The reset pulse is derived from the NOT Q output which pulses the reset line (via transistor Q1) to clear all other latches whenever the Q output is set.
Components R3, Q1 and R2 form the common reset circuit and, therefore, should not be be repeated. Additional latches connect into the reset circuit
at the points marked with the red dots.
A single CMOS 4011 Quad NAND gate IC handles the logic.
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