Facebook
Google
GitHub
Linkedin
Hey I wanted to get some input on a circuit for a multi phase buck converter. There are quite a few things I've been wondering that might be common knowledge. I've started messing around with Eagle and it's clear that it won't be too hard to design the circuit board once I've figured out a good topology and operating principles. My goal for this module is to build a compact buck style voltage controller, with a topology that supports n phases. I'll be switching P channel mosfets through inductors to produce voltage off of the G(-) rail. It provides constant output voltage regulated to an input reference voltage and so far with a single phase one I've had good luck regulating voltage under extremely variable PWM load. So perhaps I'll start with some questions: Perhaps I should number them. Please answer any that suit you.
1.) I know that because of harmonics, having a prime number of phases is ideal, but electronics components often come in 2,4 or 6 per package, with some odd number variants wasting pins and board space. So is having three phases better than four, five better than six, seven better than eight? Would the harmonic help more or less as the number of phases increased?
2.) I can see the benefit of going to multi phase drive.
If I'm driving 5A through 300mOhm of mosfet on and coil resistance, my conduction losses will be I^2*R=7.5W
If I'm using a 5 phase design at the same output voltage and current load, I have 5 phases, each conducting 1A on average, and each dissipating 1.5W. To produce this dissipation, each phase would have about R=P/I^2 1.5 ohms. Any resistance less than this would represent a savings in power
dissipation. One part I'm not quite sure of is that because having 5 phases will divide the ripple by 5, can the inductance on each phase be reduced to 1/5 of the inductance of the single inductor design, or is this relationship nonlinear?
Going to a higher resistance PMOS, will allow lower gate charge and faster switching times, and thus a higher frequency, even lower inductance per phase, and a choice of even smaller inductors or decreased resistance and more power savings.
So do I understand all of this more or less correctly?
3.) I went browsing for tiny PMOSSES, comparing a single TO-220 with ON resistance of roughly 50-70mOhm, looking to find something 1/5 the size and concluded I can solder SOT23 type chips without an oven if I have to. I found the AO3407, tiny little PMOSSES for only a few shmeckels each. Compared to the TO-220s I'd been looking at, it has 1/4 to 1/3 of the switching capacitance but for some reason still has less on resistance. I'm a bit amazed by the specs on this component as I've never considered non-thru hole chips before. What are some of your favorite cheap(Qty <=100) n and p mosfets at 30V, 50-60V and 100-200V? I've tried numerous searches along these lines but have yet to come across a list of favorite components. I like the TS555IN for 555 timers for example. I can make really fast low power circuits with it, much lower than I manage with other 555s, and the only drawback I've found thus far is low output current. I also like inverters and flip flops, logic ICs and comparators. Don't really know how to use an op amp or serial logic yet. What are your faves?
For this project the most relevant parts so far are super small pmos and nmos. D flip flops (non-differential, non-inverting). Very small signal diodes, single inverters, and a monostable multivibrator that's smaller than a 555 in case I go with an individually timed analog pulse per phase so that their conduction periods can overlap.
4.) Given that the goal in the first place is to have each phase switch faster and conduct 1/5 of the current of the larger mosfet, is it necessary for the conduction bands of the phases to overlap at all, or worse yet, would this cause cross conduction and or negative effects? Would it actually be better, provide more stable output, etc?
5.) Related to the previous, If they need not overlap, I can use a single pulse generator and simply regulate which phase it pulses. I can potentially also use a single mosfet driver rather than one per phase, assuming it didn't mind running at 5x the phase frequency. Part of the reason I like using a pulse generator is that once I've set my system frequency, the maximum pulse time will determine the maximum duty cycle and thus output power. Pulses turn on via clock signal, and are forced off when a comparator detects that the output exceeds the reference voltage. As long as I keep the frequency high enough and the inductor large enough, the output voltage remains solid under variable load, responds quickly to changes in reference voltage. If maximum pulse length is reached, output voltage will sag as necessary for the system to continue to function at this power level. If desired this intentional brownout can be used to induce shutdown in short circuit or overload conditions. If they do need to be able to overlap, the feedback mechanism must be more complicated, with the pulse length of all of the phases being controlled by something more complicated than a comparator.
The question here, is how simple could a feedback mechanism be to achieve 0-100% duty cycle regulation with equal length asynchronous pulses on 5 channels, and what sort of voltage regulation can I expect?
6.) Another option I see a bit in between is to simply have phases turn on when they receive their clock pulse, but only turn off when the comparator reports the reference voltage is reached. If the load became great enough that the duty cycle of a phase exceeded its "turn" (20% duty cycle for 5 phase) it would simply continue conducting and both would shut off when the voltage was reached. When the next kicked in, as long as the load was the same, it would run for a full duty cycle, remain conducting, and the cycle would repeat, and as far as I can see, I'm concerned that even though each phase would still receive it's clock pulse and begin conducting in turn, I would have a different effective frequency because half of the phases would be running at a higher duty cycle. This is one of the places where I can see an advantage to an odd and or prime number of phases, because for a situation where up to 2 mosfets were conducting at once, any odd number of phases would cause the mosfet that was running the higher duty cycle to alternate between states on each phase. If you got to a state where three of 5 or more mosfets were conducting at once, you would have one on for >40%, one for >20%, one for <20% duty cycle, so if you had only 3 phases, the same phase would always be at high duty cycle on its turn and risk overheating, so if you have any multiple of 2 phases when up to 2 phases will be conducting, problems could occur. If there is a chance that 3 phases will be conducting, multiples of 3 become a problem, which leaves 5 phases. A 5 phase design of this type should be OK as far as I can see for any load that would cause no more than 4 mosfets to conduct at once, which by duty cycle would mean 1/4 of the mosfets were on at most 80% of the time, 1/4 were on 60% of the time, and 1/4 were 40% and 1/4 were 20%. 1.25 mosfets * (.8+.6+.4+.2) = 2.5 mosfets conducting 100% of the time, so the maximum average conduction would be about 50% duty cycle for the whole array. I can see that the changes in current feed through would probably cause some voltage artifacts at 1/4 of the base clock frequency in this state, but assuming those are not too problematic, what other downsides might there be? As far as I understand the necessary inductance is determined by frequency, but larger duty cycle means a larger pulse, so would I need larger or better inductors in a way I don't currently understand? Otherwise this topology looks very promising as while the duty cycle would change, the frequency of each inductor would remain the same. This design eliminates the need for the 555 monostable to determine pulse length, and certainly doesn't need one plus a resistor and a capacitor per channel, using an and gate and two diodes per channel to create a latch with Out=(CurrentOut OR OnPulse) AND ShouldBeOn. ShouldBeOn is high when the output voltage is lower than the reference voltage, CurrentOut is the current output feedback so the latch stays on after the OnPulse ends.
What are your thoughts on this design?
1.) I know that because of harmonics, having a prime number of phases is ideal, but electronics components often come in 2,4 or 6 per package, with some odd number variants wasting pins and board space. So is having three phases better than four, five better than six, seven better than eight? Would the harmonic help more or less as the number of phases increased?
2.) I can see the benefit of going to multi phase drive.
If I'm driving 5A through 300mOhm of mosfet on and coil resistance, my conduction losses will be I^2*R=7.5W
If I'm using a 5 phase design at the same output voltage and current load, I have 5 phases, each conducting 1A on average, and each dissipating 1.5W. To produce this dissipation, each phase would have about R=P/I^2 1.5 ohms. Any resistance less than this would represent a savings in power
dissipation. One part I'm not quite sure of is that because having 5 phases will divide the ripple by 5, can the inductance on each phase be reduced to 1/5 of the inductance of the single inductor design, or is this relationship nonlinear?
Going to a higher resistance PMOS, will allow lower gate charge and faster switching times, and thus a higher frequency, even lower inductance per phase, and a choice of even smaller inductors or decreased resistance and more power savings.
So do I understand all of this more or less correctly?
3.) I went browsing for tiny PMOSSES, comparing a single TO-220 with ON resistance of roughly 50-70mOhm, looking to find something 1/5 the size and concluded I can solder SOT23 type chips without an oven if I have to. I found the AO3407, tiny little PMOSSES for only a few shmeckels each. Compared to the TO-220s I'd been looking at, it has 1/4 to 1/3 of the switching capacitance but for some reason still has less on resistance. I'm a bit amazed by the specs on this component as I've never considered non-thru hole chips before. What are some of your favorite cheap(Qty <=100) n and p mosfets at 30V, 50-60V and 100-200V? I've tried numerous searches along these lines but have yet to come across a list of favorite components. I like the TS555IN for 555 timers for example. I can make really fast low power circuits with it, much lower than I manage with other 555s, and the only drawback I've found thus far is low output current. I also like inverters and flip flops, logic ICs and comparators. Don't really know how to use an op amp or serial logic yet. What are your faves?
For this project the most relevant parts so far are super small pmos and nmos. D flip flops (non-differential, non-inverting). Very small signal diodes, single inverters, and a monostable multivibrator that's smaller than a 555 in case I go with an individually timed analog pulse per phase so that their conduction periods can overlap.
4.) Given that the goal in the first place is to have each phase switch faster and conduct 1/5 of the current of the larger mosfet, is it necessary for the conduction bands of the phases to overlap at all, or worse yet, would this cause cross conduction and or negative effects? Would it actually be better, provide more stable output, etc?
5.) Related to the previous, If they need not overlap, I can use a single pulse generator and simply regulate which phase it pulses. I can potentially also use a single mosfet driver rather than one per phase, assuming it didn't mind running at 5x the phase frequency. Part of the reason I like using a pulse generator is that once I've set my system frequency, the maximum pulse time will determine the maximum duty cycle and thus output power. Pulses turn on via clock signal, and are forced off when a comparator detects that the output exceeds the reference voltage. As long as I keep the frequency high enough and the inductor large enough, the output voltage remains solid under variable load, responds quickly to changes in reference voltage. If maximum pulse length is reached, output voltage will sag as necessary for the system to continue to function at this power level. If desired this intentional brownout can be used to induce shutdown in short circuit or overload conditions. If they do need to be able to overlap, the feedback mechanism must be more complicated, with the pulse length of all of the phases being controlled by something more complicated than a comparator.
The question here, is how simple could a feedback mechanism be to achieve 0-100% duty cycle regulation with equal length asynchronous pulses on 5 channels, and what sort of voltage regulation can I expect?
6.) Another option I see a bit in between is to simply have phases turn on when they receive their clock pulse, but only turn off when the comparator reports the reference voltage is reached. If the load became great enough that the duty cycle of a phase exceeded its "turn" (20% duty cycle for 5 phase) it would simply continue conducting and both would shut off when the voltage was reached. When the next kicked in, as long as the load was the same, it would run for a full duty cycle, remain conducting, and the cycle would repeat, and as far as I can see, I'm concerned that even though each phase would still receive it's clock pulse and begin conducting in turn, I would have a different effective frequency because half of the phases would be running at a higher duty cycle. This is one of the places where I can see an advantage to an odd and or prime number of phases, because for a situation where up to 2 mosfets were conducting at once, any odd number of phases would cause the mosfet that was running the higher duty cycle to alternate between states on each phase. If you got to a state where three of 5 or more mosfets were conducting at once, you would have one on for >40%, one for >20%, one for <20% duty cycle, so if you had only 3 phases, the same phase would always be at high duty cycle on its turn and risk overheating, so if you have any multiple of 2 phases when up to 2 phases will be conducting, problems could occur. If there is a chance that 3 phases will be conducting, multiples of 3 become a problem, which leaves 5 phases. A 5 phase design of this type should be OK as far as I can see for any load that would cause no more than 4 mosfets to conduct at once, which by duty cycle would mean 1/4 of the mosfets were on at most 80% of the time, 1/4 were on 60% of the time, and 1/4 were 40% and 1/4 were 20%. 1.25 mosfets * (.8+.6+.4+.2) = 2.5 mosfets conducting 100% of the time, so the maximum average conduction would be about 50% duty cycle for the whole array. I can see that the changes in current feed through would probably cause some voltage artifacts at 1/4 of the base clock frequency in this state, but assuming those are not too problematic, what other downsides might there be? As far as I understand the necessary inductance is determined by frequency, but larger duty cycle means a larger pulse, so would I need larger or better inductors in a way I don't currently understand? Otherwise this topology looks very promising as while the duty cycle would change, the frequency of each inductor would remain the same. This design eliminates the need for the 555 monostable to determine pulse length, and certainly doesn't need one plus a resistor and a capacitor per channel, using an and gate and two diodes per channel to create a latch with Out=(CurrentOut OR OnPulse) AND ShouldBeOn. ShouldBeOn is high when the output voltage is lower than the reference voltage, CurrentOut is the current output feedback so the latch stays on after the OnPulse ends.
What are your thoughts on this design?
