Hi, I am newcomer.
I post for Question.
I'm not good at English, so even though my English is awkward, please don't laugh out and understand me.
It is classical MOSFET VG fixing biasing circuit.
VDD(+15V) is divided by 8MΩ and 7MΩ for VG=+7V (Voltage divider),
VD=+10V, VS=+5V, ID=0.5mA
and RD=10KΩ, RS=10KΩ
I have question for its solution.
it says
" Observe that the dc voltage at the drain (+10V) allows for a positive signal swing of +5V (i.e., up to VDD) and a negative signal swing of -4V [i.e., down to (VG-Vt) "
I can't understand how these swings come out.
I tried to solve this problem like this.
For example, For CS Amplifier Conceptual circuit,
iD= 1/2 * Kn' * W/L * (vGS-Vt)^2
vDS=VDD-iDRD
so vDS=VDD - 1/2 * RD * Kn' * W/L * (vGS-Vt)^2
and substitute vDS=vGS-Vt into (vGS-Vt),
vDS=VDD - 1/2 * RD * Kn' * W/L * vDS^2
this VDSB is Triode-Saturation Boundary.
finally I could get swing. ( VDD ~ VDSB )
But in VG Fixing Baising Problem, VS isn't Fixed.
So, I don't know How can I.
Please help me.
I post for Question.
I'm not good at English, so even though my English is awkward, please don't laugh out and understand me.
It is classical MOSFET VG fixing biasing circuit.
VDD(+15V) is divided by 8MΩ and 7MΩ for VG=+7V (Voltage divider),
VD=+10V, VS=+5V, ID=0.5mA
and RD=10KΩ, RS=10KΩ
I have question for its solution.
it says
" Observe that the dc voltage at the drain (+10V) allows for a positive signal swing of +5V (i.e., up to VDD) and a negative signal swing of -4V [i.e., down to (VG-Vt) "
I can't understand how these swings come out.
I tried to solve this problem like this.
For example, For CS Amplifier Conceptual circuit,
iD= 1/2 * Kn' * W/L * (vGS-Vt)^2
vDS=VDD-iDRD
so vDS=VDD - 1/2 * RD * Kn' * W/L * (vGS-Vt)^2
and substitute vDS=vGS-Vt into (vGS-Vt),
vDS=VDD - 1/2 * RD * Kn' * W/L * vDS^2
this VDSB is Triode-Saturation Boundary.
finally I could get swing. ( VDD ~ VDSB )
But in VG Fixing Baising Problem, VS isn't Fixed.
So, I don't know How can I.
Please help me.
