Hello All,
I do not understand why the MOSFET conducts for the negative cycle of applied input even though there's no voltage applied at the gate (PWM configured). Another thing why is the voltage at the point just above the MOSFET similar to input even though there's current flowing through the load. Shouldn't the voltage at that point be less than applied input because some voltage is dropping across the load? What am I missing?

 

I do not understand why the MOSFET conducts for the negative cycle of applied input even though there's no voltage applied at the gate

Notice that arrow on the MOSFET symbol.
That shows the forward direction for the parasitic drain-source substrate diode, which becomes forward biased for a negative drain-source voltage N-MOSFET.

Shouldn't the voltage at that point be less than applied input because some voltage is dropping across the load?

Only when current is going through the load, giving an IR drop.

 

Notice that arrow on the MOSFET symbol.
That shows the forward direction for the parasitic drain-source substrate diode, which becomes forward biased for a negative drain-source voltage N-MOSFET.
Only when current is going through the load, giving an IR drop.

The current is actually going through the load but there's no drop.

 

The current is actually going through the load but there's no drop.

Not possible.

 

Not possible.

Exactly, But in the graph, there's a current through the load throughout the negative cycle

 

To drive the gate properly, the V6 voltage should be between the gate and source of the FET: not between gate and ground.

 

That must be the worst-drawn bridge rectifier I've ever seen.

 

To drive the gate properly, the V6 voltage should be between the gate and source of the FET: not between gate and ground.

Yes, but that does not solve the issue of conducting in negative cycle. I tried that.

 

That must be the worst-drawn bridge rectifier I've ever seen.

I know lol

 

I know lol

Well lol, since I'm not into trying to understand poorly drawn schematics, I suggest you redo it in the normal manner, if you want further comment from me.

 

Yes, but that does not solve the issue of conducting in negative cycle. I tried that.

Works ok in my sim.
Your plots are using voltages relative to ground, but your FET source is not at ground potential. That's why you get the results you're seeing.
Move the ground symbol to the FET source and your results will magically be as you'd expect.
The sim will run faster if you use 'real' diodes instead of those default ones.

 

Hi Salman,

With PWM, MOSFETs can conduct without gate voltage due to gate capacitance. Consider threshold voltage and gate charge. Load current causes voltage drop, but MOSFET area may still show input voltage due to parasitic elements. This can lead to unexpected behaviour.

 

Works ok in my sim.
Your plots are using voltages relative to ground, but your FET source is not at ground potential. That's why you get the results you're seeing.
Move the ground symbol to the FET source and your results will magically be as you'd expect.
The sim will run faster if you use 'real' diodes instead of those default ones.

So I've got it working for the positive cycle but for the negative cycle, the source is almost always at lower potential than the gate which results in continuous conduction for the negative cycle. Is there any way I can control conduction just like in positive cycle?

 

Keeping the MOSFETs off during the negative half cycle requires a little magic.
Below is an example circuit:
Basically you need to connect the gates to 10V to turn them on, and then open circuit the signal to the gates so that the gate-source resistor keeps the MOSFET gate-source voltage at 0V to turn them both off .
This circuit uses a high voltage PNP BJT in a common-base configuration to perform that function.
It applies the 10V control signal to the MOSFET gates when on, but basically open circuits the connection to the gates when off.
This allows the gates to go below 0V (green trace), thus letting R2 keep the MOSFETs' Vgs at zero (purple trace), and keeping M2 off during the negative half cycle.
For the negative half cycle, the source is maintained near the negative voltage by conduction through M1s substrate diode.

The gate stays at 0V for the positive half cycle, since that keeps M1 off.

The BJT as well as the MOSFETs must have a voltage rating higher than the peak value of the sinewave supply.



A high-voltage P-MOSFET could be used in place of the BJT if desired.
For that you could eliminate R3 and connect the gate directly to ground, with source as input and drain as output (below).

 

Keeping the MOSFETs off during the negative half cycle requires a little magic.
Below is an example circuit:
Basically you need to connect the gates to 10V to turn them on, and then open circuit the signal to the gates so that the gate-source resistor keeps the MOSFET gate-source voltage at 0V to turn them both off .
This circuit uses a high voltage PNP BJT in a common-base configuration to perform that function.
It applies the 10V control signal to the MOSFET gates when on, but basically open circuits the connection to the gates when off.
This allows the gates to go below 0V (green trace), thus letting R2 keep the MOSFETs' Vgs at zero (purple trace), and keeping M2 off during the negative half cycle.
For the negative half cycle, the source is maintained near the negative voltage by conduction through M1s substrate diode.

The gate stays at 0V for the positive half cycle, since that keeps M1 off.

The BJT as well as the MOSFETs must have a voltage rating higher than the peak value of the sinewave supply.

View attachment 305285

A high-voltage P-MOSFET could be used in place of the BJT if desired.
For that you could eliminate R3 and connect the gate directly to ground, with source as input and drain as output (below).

Thank you, this really is magic. If I understand correctly, this makes the potential difference between gate and source zero unless a signal is applied a the gate?

 

this makes the potential difference between gate and source zero unless a signal is applied a the gate?

Basically yes, as long as no-signal-to-the-gate is an open circuit, not zero voltage.