I'm designing an H-Bridge to handle 24v and up to 2A loads. The MOSFET gate operation is controlled by a TTL logic signal that is level shifted by a BJT so that Vgs = Vds when the device is on. My understanding is that this forces the MOSFET to either be off or in saturation mode.

What concerns me is what is Vgs actually going to be under various motor loads; If I use a part with a 20v gate oxide breakdown voltage is the MOSFET going to breakdown if the motor stalls giving a Vgs = ~24v

Or should I stick a voltage divider in there and supply the gate with a voltage around where the RDS(on) curve flattens out.

 

I'm designing an H-Bridge to handle 24v and up to 2A loads. The MOSFET gate operation is controlled by a TTL logic signal that is level shifted by a BJT so that Vgs = Vds when the device is on.

My understanding is that this forces the MOSFET to either be off or in saturation mode.

What concerns me is what is Vgs actually going to be under various motor loads; If I use a part with a 20v gate oxide breakdown voltage is the MOSFET going to breakdown if the motor stalls giving a Vgs = ~24v

Or should I stick a voltage divider in there and supply the gate with a voltage around where the RDS(on) curve flattens out.

Well, I took a look at your schematic, and I think you may be confused about a few things.

First, you have your P-ch and N-ch MOSFETs reversed; that is, the N-ch need to be on the low side, and the P-channels on the positive side.

Secondly, the use of "Vss". I know it's confusing when you first start designing circuits; I've been there!

But basically:
Vcc, Vdd, V+, +V, etc. are usually considered positive voltages with respect to the ground reference point.

Vee, Vss, V-, -V, etc are usually considered negative voltages with respect to the ground reference point.

Note that Vdd, Vcc and Vee, Vss are given in regards to NPN transistors or N-channel MOSFETs. Many years ago, PNP transistors were the order of the day; but since the early 70's, NPN's have been the preferred devices - this is because electrons can travel through silicon more quickly than holes.

Note that with P-ch MOSFETs, you normally draw them with the source terminal on top, drain on the bottom. N-ch MOSFETs get drawn with drain on top, source on the bottom.

Similar with transistors; NPN goes collector up, emitter down; PNP goes collector down, emitter up.

This is all because the basic "rules of thumb" for schematics are:
1) More positive voltages towards the top, more negative voltages towards the bottom.
2) Inputs come from the left, outputs flow towards the right.

There are always exceptions to such "rules of thumb". In this case, since the bridge has two sides that are mirror images, mirroring makes perfect sense.

Once you get all of that digested, you have another problem remaining; you won't be able to turn your P-ch MOSFETs off once you get them turned on. You will need to use an open-collector driver or level translator to do that.

 

So I fixed and cleaned the schematic. I really goofed on the MOSFETs; they were even reversed in my simulations.

The open collector issue... my guess is you were looking at it from the point of view when I had the MOSFETs reversed, becuase I am pretty sure that the pFETs have open collectors attached to them; and likewise the nFETs have line drivers.

Now from my simulations I see that Vgs ≈ Vdd when the motor is stalled (Zmotor ≈ 0); assuming there is nothing else suspect about the circuit; should I reduce the gate voltage or should I look for a more robust component to avoid the gate oxide breakdown?

Thanks a lot for your help!

 

So I fixed and cleaned the schematic. I really goofed on the MOSFETs; they were even reversed in my simulations.

That's OK, it's a REALLY easy mistake to make.

Keeping the pin labels turned on will help a lot in the beginning. Then start off by orienting the FET so that the gate is pointing to the left (remember; inputs from the left... outputs flow towards the right). Once you have the gate pointed left, things get easier. If the arrow is pointing towards the gate, it's an N-ch FET, so the source terminal belongs at the bottom; if the arrow is pointing away from the gate, it's a P-channel, so the source goes up.

The open collector issue... my guess is you were looking at it from the point of view when I had the MOSFETs reversed, becuase I am pretty sure that the pFETs have open collectors attached to them; and likewise the nFETs have line drivers.

OK, that part isn't going to work well at all. 1MEG is a ridiculously high value for a pull-up resistor. It'll take a half-hour for the pair of gates to charge up (not really, but it will be a LONG time for a switch to turn on).

Now from my simulations I see that Vgs ≈ Vdd when the motor is stalled (Zmotor ≈ 0); assuming there is nothing else suspect about the circuit; should I reduce the gate voltage or should I look for a more robust component to avoid the gate oxide breakdown?

Well, your approach is a bit off, I'm afraid.

Have a look at the attached. The Zener diodes keep the P-ch MOSFET gates within 10v of their drain. The N-ch MOSFETs are logic-level, so they can be driven by the 74HC132's directly, unless you are planning on using PWM at more than a couple hundred Hz.

Note that I'm using 74HC132's instead of 7400's; the 132's are Schmitt triggers. Note that you can also wire them as inverters. Now if you wanted to just use a single quad Schmitt-trigger NAND gate, the NAND labeled U3 could be replaced by an NPN transistor used as a logic inverter; emitter to ground, collector to 5v via a 1k resistor, and a 4.7k resistor on the base.

In the attached schematic, the Vdd of the 74HC132 is not shown; it's 5v and it's part of the model. Neither have I shown bypass caps for it.

 

Just trying to wrap my head around your circuit, so let me start with explaining how I think the pFET part of the circuit.

When the logic input is low for a long time, the voltage at node A is equal to the voltage at node B.

When the logic level shifts from low to high the voltage at node A will decay at some function of time to the voltage at node B minus to the zener voltage of the diode.

When the logic high voltage has settled and shifts to logic low the voltage at node A will grow at some function of time until the voltage at node A reaches the voltage at node B.

And in regards to the schottky diodes; are they necessary considering the MOSFETs have them intrinsically?

 

In your diagram, R1 should be 1k Ohms. If the transistor is turned off, the gate of the MOSFET will be charged to the same potential as the source terminal, turning the MOSFET off. The time it takes to do so will be dependent upon the gate capacitance.

In your diagram, R2 should be 620 Ohms. When the transistor turns on, the gate is discharged via R2 until the voltage across the Zener reaches about 10v. Then the remaining voltage is dropped across R2. You'll see about 22.6mA current through R2 when the transistor is turned on.

Yes, the Schottky diodes are necessary. Sure, the MOSFETs have body diodes. However, it's better to keep the MOSFETs cool and not depend on the body diodes to take care of the reverse EMF.