Circuit:
http://i812.photobucket.com/albums/zz41/uofmx12/ckt2.jpg

Why is it, the output is 5V when the input A is grounded?

 

Note that you've got Q2 and Q3 "upside-down" (i.e. their sources and drains should be swapped).

If you do this, then the circuit is a nand gate, so with 0V on either input the output is +5V - otherwise (with both inputs at +5V) the output is at 0V.

For the output to be at 0V, the bottom two mosfets need to be turned on, and this is achieved when both gates are taken to +5V. In this situation, the top two (p-channel) mosfets are off, since their gates and sources are at the same voltage.

I'll let you figure out what happens when either input is taken to 0V...

 

Note that you've got Q2 and Q3 "upside-down" (i.e. their sources and drains should be swapped).

If you do this, then the circuit is a nand gate, so with 0V on either input the output is +5V - otherwise (with both inputs at +5V) the output is at 0V.

For the output to be at 0V, the bottom two mosfets need to be turned on, and this is achieved when both gates are taken to +5V. In this situation, the top two (p-channel) mosfets are off, since their gates and sources are at the same voltage.

I'll let you figure out what happens when either input is taken to 0V...

Yes, I did have it wrong but I knew it was a NAND gate. When both inputs are at 5V it is about 13.48pV which is 0 output. When either input is 0V it is still 5V. But not sure why.

 

With either input at 0V, both upper transistors will be on (they're p-channel, so they'll conduct with their gates sufficiently negative with respect to their sources). Equally, since one of the bottom transistors has its gate tied to 0V it can't conduct, the output can only be at +5V.

Of course, as you go from 0 to 5 at the input (or vice-versa) there may be a point at which all transistors are very briefly conducting, but that's another story.