Yes, I did have it wrong but I knew it was a NAND gate. When both inputs are at 5V it is about 13.48pV which is 0 output. When either input is 0V it is still 5V. But not sure why.Note that you've got Q2 and Q3 "upside-down" (i.e. their sources and drains should be swapped).
If you do this, then the circuit is a nand gate, so with 0V on either input the output is +5V - otherwise (with both inputs at +5V) the output is at 0V.
For the output to be at 0V, the bottom two mosfets need to be turned on, and this is achieved when both gates are taken to +5V. In this situation, the top two (p-channel) mosfets are off, since their gates and sources are at the same voltage.
I'll let you figure out what happens when either input is taken to 0V...
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