The bias point depends on the particular characteristics of the transistor and the amplifier, such as voltage, current, impedance, gain required.

The Q point is decided by looking at those and choosing a spot on the curve that will keep a BJT in the linear area (or a MOSFET in saturation). The Q Point will move higher or lower for Class AB/B and C amplifiers, see the e-book for details:

http://www.allaboutcircuits.com/vol_3/chpt_4/4.html

http://www.allaboutcircuits.com/vol_3/chpt_4/8.html

 

The bias point depends on the particular characteristics of the transistor and the amplifier, such as voltage, current, impedance, gain required.

The Q point is decided by looking at those and choosing a spot on the curve that will keep a BJT in the linear area (or a MOSFET in saturation). The Q Point will move higher or lower for Class AB/B and C amplifiers, see the e-book for details:

http://www.allaboutcircuits.com/vol_3/chpt_4/4.html

http://www.allaboutcircuits.com/vol_3/chpt_4/8.html

Thanks thatoneguy, but I did already take a look at the quiescent point in the AAC e-book. I understand that for class A operation, the bias point should be halfway on the graph according to the current. However, I don't see that kind of graph so maybe they just list the information?

Austin

 

I dont understand how come the MOSFET dissipates less heat in saturation region, for a given current?

VDS_Saturation_Region > VDS_Linear_Region
=>
P_Saturation_Region > P_Linear_Region

(For a given current IDS).

 

You could look at the Rds figure which gives the device's internal resistance when in full conduction. To look at an IRFP450, it is .4 ohm. Many other FET's have lower Rds figures. The power dissipated is given by I^2*R. The lower R is (Rds), the less power dissipated for a given current.

 

I agree with what you said.
Now i want to prove to you that in the linear region, RDS is smaller than in saturation region.

Look at the following graph.
As VGS increases, RDS_ON decreases.

Moreover, when VGS gets large enough, then the MOSFET is not in saturation region anymore, but gets into the linear region.

Therefore, I conclude:
RDS(triode) < RDS(saturation)

 

in the linear region, RDS is smaller than in saturation region

After some Vgs, Rds gets no smaller. As the device can no longer change conductance with an increase in Vgs, the FET must be in full conduction. This corresponds to saturation on a BJT.

Rds is therefore greater in the linear region, where conductance varies with Vgs.

 

Rds is therefore greater in the linear OHMIC region, where conductance varies with Vgs.

Using the term Ohmic Region clears up the confusion a bit with regard to the BJT "linear region or saturated region". I believe the terminology and the assumption that saturated = on is where the confusion arises.

 

Electr, you are correct, except for the statement

when VGS gets large enough, then the MOSFET is not in saturation region anymore, but gets into the linear region.

This is true only if the load resistance is high enough to allow the device to get into the linear region. As an extreme example, consider what happens if Rload=0. Then the load line is vertical.