How do we monitor the HV (1kV, 500 uA). The ADC usually have 0 to 5 V or 0 to 3.3V as voltage range for input analog signals. How we can monitor such a high voltage in FPGA using ADC ?

 

Use a resistive voltage divider and a differential amplifier.

 

The voltage divider will need to be in the range of 10 to 100 MOhms, depending on how much current you can spare. And you will need an opamp with very low bias current to buffer amplify it before the ADC.

 

In addition to the above, be careful to drop the 1KV across maybe 10 equal value 1.0Mohm or 10Mohm resistors before the smaller final value resistor across which you are planning to drop maybe 3.0V to ground. Resistors are typically rated for a maximum voltage of 200V but I'd recommend a minimum safety margin of at least a factor of two. And ensure sufficent space between the joins to avoid flash over.