Hi all ,
I'm a new here , it's my first post . i wrote a lot of testbeches controled by TCL .
This testbenches works good and powerful ,
but this testbenches cost more time because of the interaction between Tcl and the modelsim .
what i need here if there is anyone konws how to speed the TestBench by using
nifty tricks for interaction between a running VHDL
sim and a Tcl program using pipes,
Thanks
I'm a new here , it's my first post . i wrote a lot of testbeches controled by TCL .
This testbenches works good and powerful ,
but this testbenches cost more time because of the interaction between Tcl and the modelsim .
what i need here if there is anyone konws how to speed the TestBench by using
nifty tricks for interaction between a running VHDL
sim and a Tcl program using pipes,
Thanks