Hello. My task is to simulate asynchronous negative-edge triggering counter modulo 9. So far I managed to make everything mentioned before except for modulo operation. I'm not sure why my idea is not working - I want to check when there will be 1011 binary combination representing 11 in decimal and then send CLR to every flip-flop. I'm using NAND gate to propagate logical low level.
Also I would like to convert output to Aiken code. Will it be enough if I would just simply make BCD-Aiken conversion on the output?

 

What is the maximum count for a modulo 9 counter?

 

I meant mod 11, it's a typo.

 

What count is the counter resetting at?

 

I tried with another approach - using D flip-flops.


And now it counts from 15 to 12 and resets. Output:


AND gate should send 1 to reset flip-flops (When tried NAND gate, there were low state for the whole time). As it should reset at 1011, I inverted Q1 signal to trigger AND.

 

Do everyone a favor and label your bits using normal convention; Q0 LSB, Q3 MSB. And arrange the waveforms in ascending or descending order.

 

Sure, it's fixed now. Scheme:

Output:

(wej was some leftover, it's gone now)

 

Do you want the counter to count down?

 

Yes.

 

Then wouldn't you need to preset 10 into the counter at startup and again when the counter counted down to zero?

What are the requirements for implementing a BCD-Aiken converter? Do you need both output formats?

 

You're right, I should invert output from second and last flip-flop to start with. So whats left is connect every output to NAND gate and when there will be 1111 signal, NAND will send binary 0, and then I need propagate 1010 from the begging, using Preset and Clear inputs, right? From what I understand, I sholud send preset signal to Q1 and Q3 to get binary 1 on the output, and for the rest Clear signal.

I was thinking about BCD-Aiken and it won't be so hard, as I only need one output, after conversion and I already know how to do that.