Hi to everyone! I can't understand why in hard switching there is Miller plateau but no presence of it in soft switching. I don't know if I'm thinking well considering Miller plateau effect: when, for example in the high-side FET turn-on with high load, when ids = iL, vgs = Vth + iL/gm and so it remains constant during vds reaches zero. But why in soft switching it doesn't happen? I read that I have to consider the polarity of Cgd: in hard switching vgd goes from negative to positive values while in soft switching it remains always positive. How can I connect the two things?
Thanks!

 

Hi to everyone! I can't understand why in hard switching there is Miller plateau but no presence of it in soft switching. I don't know if I'm thinking well considering Miller plateau effect: when, for example in the high-side FET turn-on with high load, when ids = iL, vgs = Vth + iL/gm and so it remains constant during vds reaches zero. But why in soft switching it doesn't happen? I read that I have to consider the polarity of Cgd: in hard switching vgd goes from negative to positive values while in soft switching it remains always positive. How can I connect the two things?
Thanks!

Hi,

Are you talking about the plateau itself or the effect on the Vds?
Any gm will make it easier for Vds to change into an open load while with a heavy load the plateau will act as a form of current regulation. I would expect to see the plateau in both cases though but a sim would clear this up quick.
In any case we can look at this in more detail if you like. Simulators make this kind of study easy these days

 

Hi,

Are you talking about the plateau itself or the effect on the Vds?
Any gm will make it easier for Vds to change into an open load while with a heavy load the plateau will act as a form of current regulation. I would expect to see the plateau in both cases though but a sim would clear this up quick.
In any case we can look at this in more detail if you like. Simulators make this kind of study easy these days

Hi MrAl and thanks for the answer. Yes, I'm talking about the plateau and its effect on vgs that becomes flat in high switching and continues exponentially to Vdr in soft switching, turn-on speaking. I think that I can't understand the miller plateau effect.

 

Hi MrAl and thanks for the answer. Yes, I'm talking about the plateau and its effect on vgs that becomes flat in high switching and continues exponentially to Vdr in soft switching, turn-on speaking. I think that I can't understand the miller plateau effect.

Hello again,

Ok well think of this as a current regulator regulating the current through the capacitor or a voltage regulator regulating the voltage gate to source.
If you have a high gain the current through the capacitor will be well regulated, but if you have a low gain the current will not be regulated as well so it will start to slope, losing it's flat appearance.

But i am assuming you understand the Miller feedback capacitor principle. As the output ramps down, ti pushes current through the cap and since the cap is connected to the input and the current is the opposite of what drives the gate, the current reduces and if it reduces too much the drain stops changing, and so this has the effect of regulating the voltage at the gate.
This action depreciates when there is another current hog taking some of the current away from the regulating process and so the regulation becomes poor and so the flat parts starts to look like a ramp and since the gate is already ramping it looks like nothing has changed.
In reality however you would have to have just the right load, just the right gate drive, just the right gm, just the right Vth, just the right Vcc, and just the right load, to see a complete loss of that flat part although it may be hard to see sometimes.

I invite you to do a couple simulations with a simple mosfet switching circuit like a buck where you can experiment with either driving an inductor as in a buck or driving a heavy resistive load using a mild gate current. Look at the gate voltage and the drain voltage and think about how a voltage regulator operates in closed loop. That's what it really ends up being: a closed loop voltage regulator for a very short period of time and that is the time of the plateau.
If you like you can even experiment with an external cap between drain and gate just to see how the Miller capacitance changes things. The larger the cap value the bigger the effect. It is after all an integrator. In fact, you can also get an idea how this works by looking at an op amp integrator circuit.

 

Hello again,

Ok well think of this as a current regulator regulating the current through the capacitor or a voltage regulator regulating the voltage gate to source.
If you have a high gain the current through the capacitor will be well regulated, but if you have a low gain the current will not be regulated as well so it will start to slope, losing it's flat appearance.

But i am assuming you understand the Miller feedback capacitor principle. As the output ramps down, ti pushes current through the cap and since the cap is connected to the input and the current is the opposite of what drives the gate, the current reduces and if it reduces too much the drain stops changing, and so this has the effect of regulating the voltage at the gate.
This action depreciates when there is another current hog taking some of the current away from the regulating process and so the regulation becomes poor and so the flat parts starts to look like a ramp and since the gate is already ramping it looks like nothing has changed.
In reality however you would have to have just the right load, just the right gate drive, just the right gm, just the right Vth, just the right Vcc, and just the right load, to see a complete loss of that flat part although it may be hard to see sometimes.

I invite you to do a couple simulations with a simple mosfet switching circuit like a buck where you can experiment with either driving an inductor as in a buck or driving a heavy resistive load using a mild gate current. Look at the gate voltage and the drain voltage and think about how a voltage regulator operates in closed loop. That's what it really ends up being: a closed loop voltage regulator for a very short period of time and that is the time of the plateau.
If you like you can even experiment with an external cap between drain and gate just to see how the Miller capacitance changes things. The larger the cap value the bigger the effect. It is after all an integrator. In fact, you can also get an idea how this works by looking at an op amp integrator circuit.

Thank you for this explanation. I'll try to follow your advices and do some simulations. I'll write here my conclusions. See you soon.

 

https://www.vishay.com/docs/73217/an608a.pdf

This is the answer that I was looking for; from page 3:

"The slope of the Miller Plateau is generally shown to have a zero, or a near-zero slope, but this gradient depends on the division of drive current between Cgd and Cgs. If the slope is non-zero then some of the drive current is flowing into Cgs. If the slope is zero then all the drive current is flowing into Cgd. This happens if the Cgd x Vgd product increases very quickly and all the drive current is being used to accommodate the change in voltage across Cgd. As such, QGD is the charge injected into the gate during the time the device is in the Miller Plateau. It should be noted that once the plateau is finished (when Vds reaches its on-state value), Cgd becomes constant again and the bulk of the current flows into Cgs. The gradient is not as steep as it was in the first period t2, because Cgd is much larger and closer in magnitude to that of Cgs."

 

https://www.vishay.com/docs/73217/an608a.pdf

This is the answer that I was looking for; from page 3:

"The slope of the Miller Plateau is generally shown to have a zero, or a near-zero slope, but this gradient depends on the division of drive current between Cgd and Cgs. If the slope is non-zero then some of the drive current is flowing into Cgs. If the slope is zero then all the drive current is flowing into Cgd. This happens if the Cgd x Vgd product increases very quickly and all the drive current is being used to accommodate the change in voltage across Cgd. As such, QGD is the charge injected into the gate during the time the device is in the Miller Plateau. It should be noted that once the plateau is finished (when Vds reaches its on-state value), Cgd becomes constant again and the bulk of the current flows into Cgs. The gradient is not as steep as it was in the first period t2, because Cgd is much larger and closer in magnitude to that of Cgs."

Hi,

Yes but what really steals the current is the load when it is not soft. The lower current means the voltage can not change as fast. So it's about current gain vs how the load draws that current.
This is why it varies with load type, because the load varies the current available for changing that capacitor.
Increase gm will also change that because then there is more current available in order to maintain the initial slope.

I meant to do an op amp equivalent model but wasnt feeling too well.