Simplify? VERY. Imagine inputs and see what outputs you get. It can be simplified to two gates. Apply a set of inputs. What will the output of the decoder be? What will the output of the adder be? What will the final output be? Apply a different set of inputs.Dear Friends
I have the above circuit with 1 decoder 3-8 and 2 full adders 2-4.
View attachment 95944
I try to make it more simple and use only logic gates. So i made the above but i am not sure that is right and is still complicated
View attachment 95945
Any help? Do i have first to make α truth table?
I'm seeing three gates (two AND gates and a NOT gate) -- might be missing something. If not for the EN input, it would only require a single NOT gate. This is assuming I'm interpreting what this "full adder 2-4" is supposed to do correctly.Simplify? VERY. Imagine inputs and see what outputs you get. It can be simplified to two gates. Apply a set of inputs. What will the output of the decoder be? What will the output of the adder be? What will the final output be? Apply a different set of inputs.
Re: 2 ANDs and an InverterI'm seeing three gates (two AND gates and a NOT gate) -- might be missing something. If not for the EN input, it would only require a single NOT gate. This is assuming I'm interpreting what this "full adder 2-4" is supposed to do correctly.
Looking at the OR gates on the output. If any input is hi the output will be high.Dear Friends
I have the above circuit with 1 decoder 3-8 and 2 full adders 2-4.
View attachment 95944
I try to make it more simple and use only logic gates. So i made the above but i am not sure that is right and is still complicated
View attachment 95945
Any help? Do i have first to make α truth table?
Oops! The truth table for your adder doesn't make sense either. That is kind of important. Is it adding four binary bits or two sets of two bits? "2-bit full adder suggests summing two sets of 2 bits. See attachment.I am really confused now. So my truth table of decoder is right but the truth table of adder is wrong. I understand that when the adder has 3 inputs will be three numbers and the outputs will be one the sum of the three numbers and the other output will be the carry.
But what about if the adder has 4 inputs and 3 outputs . The one one output will be the sum of four numbers the one will be the carry and the third? Can you give me any example of the truth table?
The words of exercice are exactly " Y1 and Y2 are two adder of 4 binary digit . try to make the circuit more simple using only logic gates
Who said that the truth table for the decoder was right? I asked you to go back and look at the effect of the EN pin and HP1729 explicitly told you what that functionality was. Does your truth table reflect that functionality?I am really confused now. So my truth table of decoder is right but the truth table of adder is wrong.
If they are adders of four 0ne-bit binary numbers, then what are the possible results of adding four one-bit binary numbers? What would the output be if the inputs are {1,0,1,0}? What is the sum of 1+0+1+0? How is that sum expressed as a three-bit binary number? What would the output be if the inputs are {1,1,1,1}?I understand that when the adder has 3 inputs will be three numbers and the outputs will be one the sum of the three numbers and the other output will be the carry.
But what about if the adder has 4 inputs and 3 outputs . The one one output will be the sum of four numbers the one will be the carry and the third? Can you give me any example of the truth table?
The words of exercice are exactly " Y1 and Y2 are two adder of 4 binary digit . try to make the circuit more simple using only logic gates
Actually, I don't think it matters for this circuit. If ANY of the four inputs to the adder is HI, then the output of the adder will be non-zero in either case, while if ALL of the four inputs are LO, then the output of the adder will be zero in either case.Oops! The truth table for your adder doesn't make sense either. That is kind of important. Is it adding four binary bits or two sets of two bits? "2-bit full adder suggests summing two sets of 2 bits.
by Steve Arar
by Gary Elinoff
by Gary Elinoff