Dear Friends
I have the above circuit with 1 decoder 3-8 and 2 full adders 2-4.


I try to make it more simple and use only logic gates. So i made the above but i am not sure that is right and is still complicated


Any help? Do i have first to make α truth table?

 

Hello,
I don't think you need a truth table, just pay little attention on how the circuit works; (specially the b2 line).
You can greatly simplify it.

 

Using only logic gates will not make it simpler as you can see. Why did you think it would?
Each of those chips have many logic functions which require many logic gates to duplicate.

 

Oh ok i understand. But is what my homework ask. Make the circuit simpler and use only logic gates. Any ideas?

 

What is the metric by which "simpler" is to be measured?

If you are trying to replicate the functionality of the original circuit using only logic gates, then don't you think that the new circuit needs to have the same four input as the original circuit. Now, some of them might not get used, but the should at least enter the block. For instance, you have left out the EN signal. At the very least, that would imply that you think it has absolutely no effect on the output. Is this actually the case?

Have you examined the function that is implemented by this circuit? Do all four inputs actually affect the output?

The best way is to examine the structure of the circuit and break it down into functional blocks. But an equally valid way is to just create a truth table and see what it does at the most basic level. It's not that hard, given that there are just four inputs and two outputs.

 

Compare your outputs to b2, don't you notice anything ?

 

mmmmm no i dont notice anything. I know my try is not right because as WBahn said i need to take 2 outputs when i have 4 inputs. What about b2? Sorry i am new in circuits and somethings i dont understand them yet

 

So take it from the basics.

First, what are the truth tables for the two types of components you are using? You need:

3-8 Decoder

EN|b2|b1|b0|d7|d6|d5|d4|d3|d2|d1|d0
0|0|0|0|?|?|?|?|?|?|?|?
0|0|0|1|?|?|?|?|?|?|?|?
0|0|1|0|?|?|?|?|?|?|?|?
0|0|1|1|?|?|?|?|?|?|?|?
0|1|0|0|?|?|?|?|?|?|?|?
0|1|0|1|?|?|?|?|?|?|?|?
0|1|1|0|?|?|?|?|?|?|?|?
0|1|1|1|?|?|?|?|?|?|?|?
1|0|0|0|?|?|?|?|?|?|?|?
1|0|0|1|?|?|?|?|?|?|?|?
1|0|1|0|?|?|?|?|?|?|?|?
1|0|1|1|?|?|?|?|?|?|?|?
1|1|0|0|?|?|?|?|?|?|?|?
1|1|0|1|?|?|?|?|?|?|?|?
1|1|1|0|?|?|?|?|?|?|?|?
1|1|1|1|?|?|?|?|?|?|?|?

2-bit Full Adder

a3|a2|a1|a0|s2|s1|s0
0|0|0|0|?|?|?
0|0|0|1|?|?|?
0|0|1|0|?|?|?
0|0|1|1|?|?|?
0|1|0|0|?|?|?
0|1|0|1|?|?|?
0|1|1|0|?|?|?
0|1|1|1|?|?|?
1|0|0|0|?|?|?
1|0|0|1|?|?|?
1|0|1|0|?|?|?
1|0|1|1|?|?|?
1|1|0|0|?|?|?
1|1|0|1|?|?|?
1|1|1|0|?|?|?
1|1|1|1|?|?|?

Now, your input labels on your full adders are somewhat ambiguous. Normally there are two tw0-bit inputs labeled a1,a0 and b1,b0.

Fill these two tables out and then we can proceed from there.

 

Decoder 3-8

I think the above is the right truth table


I am not sure at all for the above table. I have many questions first of all i know adder with 3 inputs and 1 output now its more complicated i am not sure at all. I dont understand when i have more outputs what change or is all the same? Also i know that when i have in adder more than one 1 then my output will be 1 . if i have zero 1 or one 1 then my output will be 0 am i right?

 

Go back and check out what the EN input of a decoder does.

Go look up the definition of a Full Adder. It has three inputs and TWO outputs. Two inputs are the two 1-bit numbers being added and the third input is the carry-in from the next-lower bit position. The output is the sum bit for that bit position and the carry-out to the next higher bit position. A two-bit full adder should have FIVE inputs. Two 2-bit numbers being added plus the carry-in from the next-lower bit position. There are three outputs, the 2-bit sum for those two bit positions and the carry-out to the next-higher bit position.

Until you understand the function of the components you are working with, you don't stand a chance of replicating that functionality. But hopefully you can see how showing your work, even if wrong (especially if wrong) allows us to identify the issues you need to address.

I don't know what the "2-4" in "2 full-adders 2-4" means. It's possible that your Y1 and Y2 blocks are specific functions that have been provided to you, in which case you need to provide the definition of that functionality in order for us to help you.

 

Dear Friends
I have the above circuit with 1 decoder 3-8 and 2 full adders 2-4.
View attachment 95944

I try to make it more simple and use only logic gates. So i made the above but i am not sure that is right and is still complicated
View attachment 95945

Any help? Do i have first to make α truth table?

Simplify? VERY. Imagine inputs and see what outputs you get. It can be simplified to two gates. Apply a set of inputs. What will the output of the decoder be? What will the output of the adder be? What will the final output be? Apply a different set of inputs.

 

Simplify? VERY. Imagine inputs and see what outputs you get. It can be simplified to two gates. Apply a set of inputs. What will the output of the decoder be? What will the output of the adder be? What will the final output be? Apply a different set of inputs.

I'm seeing three gates (two AND gates and a NOT gate) -- might be missing something. If not for the EN input, it would only require a single NOT gate. This is assuming I'm interpreting what this "full adder 2-4" is supposed to do correctly.

 

I'm seeing three gates (two AND gates and a NOT gate) -- might be missing something. If not for the EN input, it would only require a single NOT gate. This is assuming I'm interpreting what this "full adder 2-4" is supposed to do correctly.

Re: 2 ANDs and an Inverter
Yep
Only two inputs really matter.
Actually only two gates. An AND gate and a tri-state buffer with a low enable and a pull-down resistor on the output.

 

I don't think a tri-state gate is fair game for this problem -- usually a constraint of "simple" or "basic" gates means inverters and the two-input non-trivial symmetric functions (AND, NAND, OR, NOR, XOR, XNOR). The TS can correct me if I'm wrong.

 

Dear Friends
I have the above circuit with 1 decoder 3-8 and 2 full adders 2-4.
View attachment 95944

I try to make it more simple and use only logic gates. So i made the above but i am not sure that is right and is still complicated
View attachment 95945

Any help? Do i have first to make α truth table?

Looking at the OR gates on the output. If any input is hi the output will be high.
Looking at the Adder when is there any high out? Or maybe, when is there no high out at all?

Considering the truth table of the decoder, only one output will be high at any time. Enable must be high for any output to be enabled. (If ENA is low all outputs will be low.)

So if ENA is low all the outputs of the decoder will be low. Lows into the Adder and a low out of the OR gates.

Okay so far?

 

I am really confused now. So my truth table of decoder is right but the truth table of adder is wrong. I understand that when the adder has 3 inputs will be three numbers and the outputs will be one the sum of the three numbers and the other output will be the carry.
But what about if the adder has 4 inputs and 3 outputs . The one one output will be the sum of four numbers the one will be the carry and the third? Can you give me any example of the truth table?
The words of exercice are exactly " Y1 and Y2 are two adder of 4 binary digit . try to make the circuit more simple using only logic gates

 

q

I am really confused now. So my truth table of decoder is right but the truth table of adder is wrong. I understand that when the adder has 3 inputs will be three numbers and the outputs will be one the sum of the three numbers and the other output will be the carry.
But what about if the adder has 4 inputs and 3 outputs . The one one output will be the sum of four numbers the one will be the carry and the third? Can you give me any example of the truth table?
The words of exercice are exactly " Y1 and Y2 are two adder of 4 binary digit . try to make the circuit more simple using only logic gates

Oops! The truth table for your adder doesn't make sense either. That is kind of important. Is it adding four binary bits or two sets of two bits? "2-bit full adder suggests summing two sets of 2 bits. See attachment.

Otherwise ...
You are thinking too hard. Under what condition do you have "any high out"? Or maybe easier, when is there all lows out? These are the only two conditions that matter; "lows out" or "any high out".
.

 

I am really confused now. So my truth table of decoder is right but the truth table of adder is wrong.

Who said that the truth table for the decoder was right? I asked you to go back and look at the effect of the EN pin and HP1729 explicitly told you what that functionality was. Does your truth table reflect that functionality?

I understand that when the adder has 3 inputs will be three numbers and the outputs will be one the sum of the three numbers and the other output will be the carry.
But what about if the adder has 4 inputs and 3 outputs . The one one output will be the sum of four numbers the one will be the carry and the third? Can you give me any example of the truth table?
The words of exercice are exactly " Y1 and Y2 are two adder of 4 binary digit . try to make the circuit more simple using only logic gates

If they are adders of four 0ne-bit binary numbers, then what are the possible results of adding four one-bit binary numbers? What would the output be if the inputs are {1,0,1,0}? What is the sum of 1+0+1+0? How is that sum expressed as a three-bit binary number? What would the output be if the inputs are {1,1,1,1}?

 

Oops! The truth table for your adder doesn't make sense either. That is kind of important. Is it adding four binary bits or two sets of two bits? "2-bit full adder suggests summing two sets of 2 bits.

Actually, I don't think it matters for this circuit. If ANY of the four inputs to the adder is HI, then the output of the adder will be non-zero in either case, while if ALL of the four inputs are LO, then the output of the adder will be zero in either case.

But the supplied truth table makes no sense for any kind of adder that I can see and, if it were correct, it would make the equivalent circuit quite a bit more complex.

 

Ok the words of exercise are . We have two Adder Y1 and Y2 of four binary digits. Make the circuit simpler using only logic gates.
So my truth table of decoder 3-8 is wrong but where is the wrong? And the truth table of 4-3 adder is the above?


Can you explain me the three outputs s1,s2,s3 and how we find thesse numbers? what is the carry output, what is the sum output and what is the third?