We have a time schedule which looks like this:

Where "Data available" and "Acknowledge" are input signals and "Break" is output signal.

The circuit is going to work in a way so that when "Data available" gives a 1, "Break" should become 1 and then remain 1 until "Acknowledge" gives a 1, then "Break" turns to 0.

I have made a state diagram that looks like this:

However it says that for the state transition diagram, it will not be enough with two states, because of the two cases. But I don't see how the two cases would give different states?

How would you make this diagram, truth table and/or in the end the circuit itself?

 

Walk through Case 1 with your state diagram and draw the output that will result. Be sure to do what the diagram says to do, not what you want the system to do.

Also, look carefully at your timing diagram -- does the Break signal go LO when the ACK goes HI? Look carefully. Imagine stretching out the ACK signal so that it is much longer than shown. When would Break go LO? Now, having said that, the diagram shows Break going HI after some time delay from Data Av going HI. Perhaps that is to model propagation delays. If so, then perhaps the Break signal only appears to go LO on the falling edge of ACK. If you have a word description of the problem, rely on that.

 

Thanks!