- Joined Jun 25, 2020
1.1 For the following state graph, a circuit of the Mealy type is to be developed using T flip-flops. Then the circuit should be outlined. (Done)
1.2 Develop VHDL code that describes the state graph (three - process description) (Done)
1.3 Draw the synthesis result for the VHDL code.(Done)
I don't have a big knowledge about the state machines so if there's an explanation for this question I would be glad .
1.4 What is the potential risk when implementing a 12-state machine? How can this danger be reduced or eliminated?