LTSPICE simulation error/problem

Thread Starter

KaiL

Joined Aug 30, 2014
69
I am trying to run a LTspice simulation of this op amp I found online
http://s.eeweb.com/members/kalpana_manickavasagam/projects/2011/01/30/ASSIGNMENT-1296438312.pdf

upload_2016-11-11_13-10-44.png

This is my LTspice simulation circuit for the above circuit
upload_2016-11-11_13-13-4.png

However , I get strange result compared to the result in the pdf.
AC analysis I got this.
upload_2016-11-11_13-15-34.png

I am trying to simulate the open loop gain and output swing of the op amp but I seem to be get wrong result.
Could anyone help me check where did I do wrongly? I have attached the ltspice file here as well - draft 1.

If anyone wants to run the simulation file , you would need to insert the 3 files (CMOS035.lib , nmos_035 and pmos_035.asy) into the ltspice folder.
CMOS035.lib in the C:\Program Files\LTC\LTspiceIV\lib\sub
nmos_035 and pmos_035.asy in the C:\Program Files\LTC\LTspiceIV\lib\sym
This the link to the CMOS035.lib , nmos_035 and pmos_035.asy files
https://www.dropbox.com/sh/0yu1pxntkl8vrpn/AAAQq7zlUU1Wsfc7W5JZgNGSa?dl=0
 

Attachments

Thread Starter

KaiL

Joined Aug 30, 2014
69
You made a lot of mistakes in drawing circuitry.
View attachment 115135
Hi Thanks for your help. I tried changing the things so that it looks like the one you have shown but my simulated is still different from yours.
upload_2016-11-11_21-6-31.png
upload_2016-11-11_21-6-52.png

Is it possible to share your ltspice file?

Could I also check with you what command do I need to key in in order to check the voltage swing and differential gain?
 
Last edited:

Bordodynov

Joined May 20, 2015
3,179
You will not have seen several "+". + is a power node. The fourth pin (substrate) of p-channel transistors must be connected to the positive supply.

Draft1AC.png
 
Last edited:

Thread Starter

KaiL

Joined Aug 30, 2014
69
You will not have seen several "+". + is a power node. The fourth pin (substrate) of p-channel transistors must be connected to the positive supply.

View attachment 115141
Hi

Thanks for your help again. I have connected the fourth pin of the p-channel to positive supply but it is still slightly different. By the way , what should I key in to generate the graph to find the differential gain and voltage swing? (I am rather new to Ltspice). Sorry for all the troubles that I have caused you

upload_2016-11-11_23-42-18.png
upload_2016-11-11_23-42-36.png
 

WBahn

Joined Mar 31, 2012
30,052
You will not have seen several "+". + is a power node. The fourth pin (substrate) of p-channel transistors must be connected to the positive supply.
But note that the bulk connection of M4 and M6, in the original circuit, are NOT connected to the positive supply -- they are connected to the more positive source/drain connection of THAT transistor, which is very common for PFETs in an N-WELL process to minimize bulk-bias effects.
 

WBahn

Joined Mar 31, 2012
30,052
Hi

Thanks for your help again. I have connected the fourth pin of the p-channel to positive supply but it is still slightly different.
Well, if you won't connect up the circuit the same way that the one you are trying to replicate is, is it any wonder that it doesn't behave exactly the same? On top of that, are you using the exact same transistor models as the original circuit?
 

Thread Starter

KaiL

Joined Aug 30, 2014
69
upload_2016-11-12_10-37-20.png

The one in rectangle (red) are all connected to positive terminal while the one in rectangle (blue) are all connected to ground. Isn't it the same as the below? or have I connected it wrongly again?
 

Bordodynov

Joined May 20, 2015
3,179
But note that the bulk connection of M4 and M6, in the original circuit, are NOT connected to the positive supply -- they are connected to the more positive source/drain connection of THAT transistor, which is very common for PFETs in an N-WELL process to minimize bulk-bias effects.
Yes,N-WELL process to minimize bulk-bias effects, but there is an additional parasitic capacitance to minus supply (p-n junction -N-WELL and p). There is also a drain-source capacitance. All this will reduce the speed.
Also I do not like, do not set the important parameters of transistors. This area drains and sources and their perimeters. The result is a very optimistic result.
Kail. M1 and M3 are drawn correctly, but M2 is drawn in error. This, they say, do not believe your eyes. If you know the Spice syntax, you can see the netlist. Greatly increase the transistor M2. Look closely: there is a connection between the substrate and the source? I argue that this connection is not present. This feature LTspice. It can not directly connect the pins.
 
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