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LTspice FET Model

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OozmaKappa

Joined Dec 15, 2019
3
I'm playing with the LEVEL 1 FET model and found that there is 10 pA of leakage into both the body and the source when my NMOS is in cutoff and Vds = 10V. Does anyone know what parameters can lower this leakage? It seems to be linearly dependent on Vds but independent of Vgs. Reducing IS and leaving Rds as infinity does not reduce it. Vds << Breakdown Voltage (infinite). Here is a list of LTspice default parameters. A picture is attached.

Thank you!
 

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