Hi everyone,

The attached figure shows a simple PLL with its waveforms on each component's output node. Can anyone please tell me why is the output of the analog loop filter, v(t) is the average voltage of the pulses (if my analysis is correct). From my understanding, the loop filter is just a low pass filter which used to filter out the high frequency component from the PFD. How does it actually works?

 

Hi everyone,

The attached figure shows a simple PLL with its waveforms on each component's output node. Can anyone please tell me why is the output of the analog loop filter, v(t) is the average voltage of the pulses (if my analysis is correct). From my understanding, the loop filter is just a low pass filter which used to filter out the high frequency component from the PFD. How does it actually works?

Actually it is the dc (avg)error volt generated by the Phase Detector to control VCO in response to phase mismatches between two Phase detector inputs.

 

A low-pass filter, if it had enough poles, would put out a pure DC level which is the AVERAGE of whatever is fed into the filter. That is the way that a PWM DAC works; the low-pass filter produces the average value, while suppressing the ripple caused by the PWM fundamental frequency...

 

Hi Mike,

Can you please explain more about what you meant by having more poles in the loop filter will eventually generate a pure DC level which is the average of whatever is fed into the filter? Probably with equations or diagrams would helps me to understand more. Thanks.

 

Ok. Here is a frequency sweep of a two-pole, Sallen Key, active Butterworth filter with a cutoff of 1Hz. Note that it passes things below 1Hz unattenuated. At 100Hz, it has 80db of attenuation.

Suppose we feed it a 100Hz PWM signal which varies from 0% duty cycle to 100% duty cycle. At any given duty cycle, if we wait for the filter to settle, it will suppress the PWM carrier frequency by 80db leaving only a tiny bit of 100Hz ripple, but passing the average value of the PWM signal.

In the second sim, the input voltage source is a 1Vp-p 100Hz square wave with a duty cycle that is stepped 0%, 10%, 20%,... 100%. Note that after the filter settles, the output is 0V, 0.1V, 0.2V,... 1.0V.

The degree of ripple suppression is a function of the steepness of the filter (number of poles) and how far from the cutoff frequency the PWM frequency is...

This same principle is used in a PLL. Using the appropriate LPF, you can filter the output of the phase detector (which is a PWM signal) to get the average value to steer the VCO.

 

Wow, such a good explanation. Thanks effort of simulating. I just wish to clarify something with you. Why when the filter settles, the output will steps from 0.0V to 1.0V since the input is attenuated. Aren't it just output a fix voltage value? Or you did a transient sweep for the input voltage?

Another question is, since you mentioned the ripples and poles. What is the relationship between them? More poles means more ripples? Thank you.

 

The Pulse Width PW is stepped from 0% to 100% in steps of 10%; each PW produces one of the output levels. The PWM period is always 10mS (100Hz). The filter has a unity gain. The amplitude of the PWM is one volt, so if the PW is 4ms (40%), the DC component (the average value) of 40% of 1V is 0.4V.

More poles means steeper rolloff, means less ripple at any particular frequency past the cuttoff.

 

Ok. From the first simulation, the low pass filter only have 1 pole right? And one pole actually contributes 90 degree of phase shift right? Why is it 180 phase shift shown from the graph?

Just aside question, what's the fundamental principle behind a low pass filter to output an average voltage of a PWM?

 

Ok. From the first simulation, the low pass filter only have 1 pole right? And one pole actually contributes 90 degree of phase shift right? Why is it 180 phase shift shown from the graph?

The filter I used is a two pole filter, so it has a rolloff of -20db/decade, and a phase shift of 180 deg.

Just aside question, what's the fundamental principle behind a low pass filter to output an average voltage of a PWM?

I thought I just demonstrated that with the three posts

 

Ya, I know that it's been attenuated by the output filter and resulting an average voltage as shwon in the simulation. I am just wondering how the filter output an average voltage instead of other types of voltage (eg. different type of waveform).

 

A low-pass filter always passes the average of what ever you feed in; triangle, sawtooth, sine riding on DC offset, noise riding on DC offset, etc. That is why low-pass filters are used ahead of Analog to Digital Converters. In that case they are called an "anti-alias" filter, but the principle is the same...

 

Alright, I will take note and will have a brief study on that. Thank you so much for your explanations.