Phase Lock Loop Filter Design

Discussion in 'Homework Help' started by Almost165, May 7, 2015.

  1. Almost165

    Thread Starter New Member

    May 7, 2015
    Hello all,
    I have to design a PLL that will lock to an FSK input signal and I'm having trouble with the filter.
    Here is some information about the circuit:
    FSK Input:
    1 from the signal Gen. = 9.5kHz
    0 from the signal Gem. = 10.5kHz
    50% duty cycle at 1kHz

    Locking VCO has a range of 9kHz to 11kHz.
    At .5V it will output 10.5kHz
    At -.5V it will output 9.5kHz

    I've tried setting the cutoff frequency of the filter to 2kHz (the lock bandwidth) and the cleanest signal is with a gain of -3.33, but I still get a long rise time and slight overshoot. Here is a picture of what I'm working with:

  2. t_n_k

    AAC Fanatic!

    Mar 6, 2009
    The important consideration is probably whether your design meets some (undisclosed) specification.
    If true, then you are probably done.