In a micro, I would measure the periods of the two pulse trains by using the respective pulses to gate a much higher frequency clock (possibly derived from the cpu clock source) into two counting-registers (timers).

Use two external interrupts (or pin change interrupt) to start / stop two timers counting internal pulse rates.

The two counts can then be used to generate a pwm output to produce both digital and analog read-out (through a low-pass filter).

 

I did a very similar project. Those frequency to voltage chips work, but we moved to just using 3 ARM M0 micro controllers. Cost wise, it was not much of a price increase at all. It seems excessive, but we now have full control over what we can do.

GopherT is on to something. We also tried a PLL approach with just 2 micro-controllers. It worked as well.

 

Here is what I was talking about:

Two pulse trains coming into a switch (SW1 + SW2). They alternately charge and discharge a capacitor (C1), based on the number of pulses -> edge-trigger via C2/R3 and C3/R4.

The traces show the voltage across C1, when the ratio of the frequencies of the two pulse trains is 4x, 2x, 1x, .5x, and 0.25x.

Similar concept can be implemented with up/down counters, or digital pot with up/down inputs.

 

I tried a similar concept to that as well, but I never got very far. However, as much as I like pure EE solutions, we are in the age of digital electronics. If we do everything digitally, fixes are easier. The full analog method can be a pain if you always need to tweak resistor values (and you will probably need a form of calibration because capacitor tolerances are not favorable). If you do go that route, I urge that you implement a detect, reset and hold circuit to ensure you are not bouncing all over the place.