Logical Effort (G) and Effort (H) in Parallel

Alon123

Joined Oct 17, 2020
3
Hi Everyone,

I am struggling with this question in which I need to understand what is the route with the least effort (H).
Usually, I'm given a route but it's very simple to calculate, because all the other inputs of the logical gates are regular inputs without any logical gates connected to them, like in this example:

The main difference and what I am struggling with, is in the example above the route is clear, and the legs of the logical gates are just regular inputs..

The circuit which I need to analyze is this:

And the question is which route has the least effort (H) - A,C, or they both the same.

My hunch is that they're both the same, but I can't figure out how to calculate it.
I think the fan-out (f) is the same for both routes - 4/1=4 (I might be wrong here so please let me know if I do).
But I'm not sure how to calculate the logical effort (G) in the routes.
For example, if I look at route A, so the first logic gate is a NOT (g=1), and the next one is NAND2 (g=4/3), but, the other input of the NAND also has a NOT gate connected to it. In my opinion, this shouldn't matter (because again, g of NOT is 1). But when I look further to this route I have a XOR2 (g=4). so far, G=g1*g2*g3=1*4/3*4=16/3, and H=G*F=64/3.
But I don't think it's right, since the other input of the XOR2 is connected to route C, so it has a NOR and a NOT beforehand.

So finally - my question is how do you calculate the effort of a route, if it has more logical gates from the other input?

MrChips

Joined Oct 2, 2009
30,448
Beats me. This is all gobbledygook to me.
I have no idea of what "Logical Effort (G) and Effort (H)" means.

Are you sure you registered in the correct forum?
This forum is AAC - All About Circuits.
The circuits you have shown are not functional. What does it mean to put capacitors on the inputs of logic gates?

What school are you attending?
What course are you taking?

Papabravo

Joined Feb 24, 2006
20,985
Can you provide some semblance of a definition for Effort(H) and Logical Effort(G). I am unfamiliar with that terminology.
Also, what is with the capacitors. You would seldom see them used in that fashion in any real circuit.

Alon123

Joined Oct 17, 2020
3
Hi,
I am studying EE, and this course is called digital circuits, the subject taught is CMOS logic, so if I'm not mistaking the capacitors are representing the capacitance of the transistors.
https://en.wikipedia.org/wiki/Logical_effort
The above is the definition from Wikipedia. The letters might be different (g,G,H and so on) but the main idea is the same from what I've read. It has the same explanations for basic circuits as shown above, but doesn't direct me to a solution or an explanation to my problem.

Thanks

Papabravo

Joined Feb 24, 2006
20,985
What transistors? (the ones inside the gates) There are no (visible) transistors in your diagram.
I disagree about the available information. The Wikipedia article has everything you need to solve the problem. You just have to read it and understand it. I suspect that you don't understand it because you pointed me to the article instead of constructing a cogent explanation. Since VLSI design was never of any particular interest to me, I'm hardly surprised at never having heard of this methodology. The closest I came was working with a team building a communications ASIC where the CAD system and the floor planning tools did all that stuff for the ASIC designers. I was working on the architecture and the design verification.

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Alon123

Joined Oct 17, 2020
3
Right, but the logic gates are basically made of CMOS, like in this example:

Which is a NAND2.
From what I understand and from previous questions that I did deal with, there's no need to actually analyze the logic gates as a bunch of CMOS transistors, but I guess this is where the capacitance is coming from...

Papabravo

Joined Feb 24, 2006
20,985
Right, but the logic gates are basically made of CMOS, like in this example:

View attachment 219824
Which is a NAND2.
From what I understand and from previous questions that I did deal with, there's no need to actually analyze the logic gates as a bunch of CMOS transistors, but I guess this is where the capacitance is coming from...
Each CMOS input is drawn, and constructed on the silicon die, as a small capacitor. The MOS transistors are complementary in that one of them turns on when the input is "high" and the other turns on when the input is low "low". Unfortunately these two different types of transistors cannot be made the same size and have equal delay characteristics. In order to have the same delay characteristics, the PMOS (active low input) transistors must be fabricated with a larger silicon area.

When a gate has multiple inputs to drive, the output needs to sink or source more current to get the desired delay characteristics. this is the essence of what is going on. Reread the wiki article again, slowly and with attention to detail.