Logic High changes to Low when under load

Thread Starter

programmer6502

Joined Feb 1, 2014
132
I'm back and did some testing. (Note: the chip I'm trying to provide a chip select for is a SRAM)

First off, the inverter stays high with a 5k load. Second, I did some voltage tests of my own and here's some interesting results I got:

1) With the SRAM connected to the original CS line (provided stock from the computer) everything seems fine. The inverter's output is 3.6v, and the AND gate's output (CS 2) is 3.3v just floating.
2) With the SRAM connected to CS 2 (see my schematic) like I want, everything drops. The inverter's output is now 1.6v, and the AND gate's output is 1.3v. So an exact 2 volt drop in those signals!
3) With the SRAM's CS pin just floating by itself, I get the same result as #2 with the gates.

Sounds like my problem might not be the gates after all since just simply allowing the SRAM's CS pin to float causes the same problems as it does connected to CS 2....
 

dl324

Joined Mar 30, 2015
16,845
1) With the SRAM connected to the original CS line (provided stock from the computer) everything seems fine. The inverter's output is 3.6v, and the AND gate's output (CS 2) is 3.3v just floating.
Outputs don't float.
2) With the SRAM connected to CS 2 (see my schematic) like I want, everything drops. The inverter's output is now 1.6v, and the AND gate's output is 1.3v. So an exact 2 volt drop in those signals!
3) With the SRAM's CS pin just floating by itself, I get the same result as #2 with the gates.
What is your supply voltage? Is the computer memory subsystem operating at something lower than 5V?
 

dl324

Joined Mar 30, 2015
16,845
Outputs floating are ok, because they won't affecting anything, but the inputs can't let them floating, because they will cause oscillation and noise.
Hi Scott,

You mean unconnected...

I meant that the outputs are actively driven and should be at one of the specified logic ranges; unless they're tri-stated or are open collector. I thought about editing my post to reflect that, but the discussion is about 74LS08 and 74LS14 which have totem pole outputs that don't float and aren't tri-stat.
 

ScottWang

Joined Aug 23, 2012
7,397
Hi Scott,

You mean unconnected...

I meant that the outputs are actively driven and should be at one of the specified logic ranges; unless they're tri-stated or are open collector. I thought about editing my post to reflect that, but the discussion is about 74LS08 and 74LS14 which have totem pole outputs that don't float and aren't tri-stat.
Hi dl:
Yes, unconnected, in logical ic or analog ic, whatever the inputs pin or the control pin of tri-state, if the pins unused we can't let them float, but the outputs are ok, floating pins maybe cause something bad we don't like.

Float - unconnected pins, normally input pins should be connect to high or low or a signal, most of oc or od floating just two states, the one is low, another is high impedance, it won't affecting itself or other components, and its output states are depend on the inputs, so the input is more important.
 

Thread Starter

programmer6502

Joined Feb 1, 2014
132
All voltages are slightly above 5v. Around 5.02 for the sub system stuff, and 5.06 for the rest of the computer.

Good information about floating pins. I learn at least one significant thing every time I come here! Though the datasheet for the AND gate (found here), seems to allow one of the two inputs to float in the truth table and come up with an output. This isn't of any importance here, I just wanted to throw it in. As for my SRAM's CS pin, clearly that's unacceptable!

Edit: I guess "X" in the truth table is actually referring to high or low
 
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dl324

Joined Mar 30, 2015
16,845
When you're getting unexpected results, measure the inputs/outputs of the offending gate and the VCC pin on the chip. If that checks out, do the same for the logic driving the inputs or being driven by the outputs.
 

Thread Starter

programmer6502

Joined Feb 1, 2014
132
At the time of the unexpected results, the voltages on all of the suspect chips is at or above 5v. For the gates themselves, the inverter's input from A15 is 2.3v, output 1.8v. The AND gate inputs the output of the inverter of course which doesn't change, along with CS measuring 3.8v (which is fine). The output of the AND gate then outputs 1.3v going to the SRAM because of the low input from the inverter. Everything acts exactly as it would if the SRAM's chip select was not connected period!

I don't know if this is likely, but maybe there's a problem with timing. The RAM is located at the beginning of memory and is one of the first tasks of the CPU. Maybe the logic (or part of it) is too slow and the CPU sees that the RAM isn't enabled in time of need and halts.
 

dl324

Joined Mar 30, 2015
16,845
inverter's input from A15 is 2.3v, output 1.8v.
VT+ for LS14 is 1.4-1.9V and LO output is 0.4V max, so something is wrong.
The AND gate inputs the output of the inverter of course which doesn't change, along with CS measuring 3.8v (which is fine). The output of the AND gate then outputs 1.3v going to the SRAM because of the low input from the inverter.
LO input for LS08 is 0.8V max, HI input is 2.0V min, so the output is indeterminate. You need to fix the problem with that signal before you can proceed.
I don't know if this is likely, but maybe there's a problem with timing. The RAM is located at the beginning of memory and is one of the first tasks of the CPU. Maybe the logic (or part of it) is too slow and the CPU sees that the RAM isn't enabled in time of need and halts.
How can that affect the level of A15 or the operation of the inverter?
 

Thread Starter

programmer6502

Joined Feb 1, 2014
132
VT+ for LS14 is 1.4-1.9V and LO output is 0.4V max, so something is wrong.
LO input for LS08 is 0.8V max, HI input is 2.0V min, so the output is indeterminate. You need to fix the problem with that signal before you can proceed.
How can that affect the level of A15 or the operation of the inverter?
No I agree. I'm just stumped. I don't understand why the single would act like that!
 

Thread Starter

programmer6502

Joined Feb 1, 2014
132
Here's a little background. The computer had 16k of DRAM, which was too small for many applications so I decided to upgrade it with SRAM since the DRAM needed for the task has become somewhat scarce. With a 32k SRAM I had on hand, I was able to get the computer to boot and run using 16k of it, using the original CAS line from the DRAM as a chip select. I was also able to figure out how to modify the old CAS line to address up to 64k (which will allow the computer to see all 32k of my SRAM before maxing out and crashing). With the intentions of getting a bigger SRAM to take full advantage of the 64k, I decided it would be a good learning experience to make some logic that would drive my 32k chip by using the modified 64k CAS/CS line and something that would limit it from going over 32k. Hence, the logic I made up in my first post. Yes it's pointless since I'm going to get a bigger chip in the long run, but you can't put a price on experience!
 
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MMcLaren

Joined Feb 14, 2010
861
You say you're using a left-over AND gate on the board... wouldn't the original designers have wired those inputs to VCC or GND?
 

sailorjoe

Joined Jun 4, 2013
364
I've read all the earlier posts and I believe you have either a short circuit somewhere or you are drawing too much power from your power supply with the extra RAM. If you look at the data sheets for your inverter and AND gate you will the expected voltages for a logic high and logic low. Your readings are very different than these. The wire lengths would likely not create the readings you have, unless the wires are shorting out somewhere. Look for an overloaded power supply, or perhaps a SRAM chip that is fried and drawing lots of power, or a missing ground connection among all the pieces. Your schematic is fine, but you have a problem not represented in the logic, it's in the implementation.

Use your voltmeter to make sure all your chips have the same ground voltage. Then make sure you still have 5 volts at each chip Vcc pin, with the SRAM chip out of the circuit and then in the circuit. Then try disconnecting the A15 ADDRESS line from your inverter, and driving it with either a pull-up resistor, or connecting it to ground with a wire. Now you have total control of the A15 lin effort and make sure your circuit works right with the line held high or low.

IIRC, the 6502 resets to a vector at the top end of memory. So the top two bytes of memory should be in ROM and are the address where you want your code to start running.

Are you modifying an old Atari or Commadore 64?
 
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