Hi,

I'm working on a project where I need to modify a chip select to only be active at the first half of a CPU's available address range, and disable once the CPU hits the next half. So, an address divider...

You can see my circuit below. What I'm working with is a 8-bit processor with the ability to address up to 64k. Here In my circuit, I have "CS" (which is active for the entire 64k range) in one of the inputs of the AND gate. Since I only want it to be active for 32k of it, I bring A15 into the picture which is connected to the input of the inverter to bring it high (since A15 alone would be low during the first half of memory). Now here's the problem. The output of the inverter is high like it should be, until it's connected to the other pin of the AND gate, when it then goes low! Why is this? Does it need a resistor or something to create a bigger load maybe?? I don't understand it. Why does the output of the inverter go low after connecting it to the AND gate? I know without a doubt that everything is connected correctly.

Help would be appreciated,

Thanks!

 

What is the type of the inverter?
If it has open collector output, a pullup resistor to Vcc is needed.

 

What are the ic numbers of inverter and AND gate?

 

If you want to split up the A15 line you can use a 74HC139.

It has 2 inputs to select up to four outputs (all normally inverting outputs). You can connect the enable line to the memory request line (if its a Z80), then the A1 input to A15 on the address line and then the A2 input to ground. Then for the first half of the address Y0 output will be low and all others high then on the second half the Y1 output will be low and all others high.

 

What is the type of the inverter?
If it has open collector output, a pullup resistor to Vcc is needed.

What are the ic numbers of inverter and AND gate?

The inveter is a 74LS14 (which is already existent on the computer board and has a free gate). The AND is a SN74LS08. I understand that there are 04 inveteres as well, the difference being from what I understand in a nutshell, is that a 14 refines it's input signals (which is probably not necessary in this case).

Anyway, I've tried using a SN series inverter to match up with the AND gate and no change. I also tired using an 04 inverter and that didn't change anything either. That was a HD74LS04P though so a little different in family. If possible, I would like to make use of that free inverter already on the board that I mentioned in the 74LS14.

 

The output of the inverter is high like it should be, until it's connected to the other pin of the AND gate, when it then goes low!

Disconnect the inverter and see if the input of the AND can be pulled HIGH with a 1K resistor to VCC.

 

If you want to split up the A15 line you can use a 74HC139.

It has 2 inputs to select up to four outputs (all normally inverting outputs). You can connect the enable line to the memory request line (if its a Z80), then the A1 input to A15 on the address line and then the A2 input to ground. Then for the first half of the address Y0 output will be low and all others high then on the second half the Y1 output will be low and all others high.

That sounds cool! There's all kinds of fancy IC's out there! I'm working with a modified 6502, so without looking I would guess that the I/0 pin would be the equivalent to what you mentioned with the Z80.

 

Disconnect the inverter and see if the input of the AND can be pulled HIGH with a 1K resistor to VCC.

Will do, need to find a resistor that size first though

 

Will do, need to find a resistor that size first though

Value isn't critical. You could use a wire; but a stuck at zero input might cause something to smoke.

 

a 14 refines it's input signals

LS14 is a Schmitt inverter that employs hysteresis to decrease rise/fall times of slow edges and/or reduce the effects of noise. This is particularly useful for CMOS where slow transitions increase power dissipation.

 

Double check the AND gate pinout. Not all gates point the same way in the package. It sounds lke you are connecting two outputs together.

ak

 

Double check the AND gate pinout. Not all gates point the same way in the package. It sounds lke you are connecting two outputs together.

ak

Just now checked again with the full chip number. Pins 1 and 2 are the inputs, and pin 3 is the output for the first gate. So nothing wrong there, but worth checking.

 

Okay, just did the resistor test. The input of the AND gate is pulled high with a 1k resistor connected to VCC.

 

What you observes isn't supposed to happen. I would check wiring, power, and parts - maybe you are trying to drive a ttl part with a cmos part, ....

one way to find out, assuming the wiring is correct, is to insert a resistor between the output and input, and measure the voltage on both ends of the resistor. It tells you who's pulling the logic low or high. Something like a 1k or a 10k resistor would do.

 

"The input of the AND gate is pulled high with a 1k resistor connected to VCC."

that means that the load present by the input pin is far less than 1k - if you specific that voltage level bs. Vcc, you know exactly how little of a load the input pin is.

which says that the output pin has very little drive, for whatever reason. That should be the focus of your debugging efforts.

 

What you observes isn't supposed to happen. I would check wiring, power, and parts - maybe you are trying to drive a ttl part with a cmos part, ....

one way to find out, assuming the wiring is correct, is to insert a resistor between the output and input, and measure the voltage on both ends of the resistor. It tells you who's pulling the logic low or high. Something like a 1k or a 10k resistor would do.

Interesting. I know for sure that everything is wired correctly, but I'll make note that the wires are somewhat long. Maybe they're picking up interference. Gonna be out and about for most of they day, so I won't be able to play with it till later.

Thanks for the help everyone!

 

What you observes isn't supposed to happen. I would check wiring, power, and parts - maybe you are trying to drive a ttl part with a cmos part, ....

OP has already stated gates are 74LS and verified connections.

 

"Maybe they're picking up interference."

assuming the right parts and wiring, no (reasonable) interference will be able to overwhelm the output.

debugging is all about challenging your assumptions and more often than not, the bugs are where you least expect it.

in that spirit, I would definitely check wiring, chip and power.

 

Are you testing on breadboard or solder on PCB?

If you testing on breadboard then change to another block and test again, you can also change the 74LS08 and test again, if you solder on PCB then change the 74LS08 and test again.

Another testing : disconnect the output of inverter, and find a 330Ω resistor to connected to the input of AND gate, another pin of resistor connected to Ground, and measure the voltage of input pin of AND gate.

 

Okay, just did the resistor test. The input of the AND gate is pulled high with a 1k resistor connected to VCC.

The inverter is supposed to be able to source 400uA. Try putting a 5K load on the inverter and see if it can maintain a HIGH output.