Hi All,

I am trying to design a circuit and have started learning about logic families. I need my circuit to run on 5V and be pretty fast (couple dozen components from input to output with propagation delay <1.4us). I first looked at the 7400 series and realized they are old and slow compared to modern chips. Would working with the 74AC logic family seem reasonable? I like the speed, rail to rail output, and large noise margins. I will need to interface to TTL differential line receivers and line drivers at each end of the circuit. Do people mix and match logic families?

Second, what is a reasonable fanout for a buffered signal in this logic family? How can I get a larger fanout if needed.

Finally, the decoding section of my circuit will use lots of inverted signals so I want to provide both inverted and non-inverted outputs from my input buffering section of the circuit. These types of outputs are described here (https://www.allaboutcircuits.com/textbook/digital/chpt-3/special-output-gates/), but I can't seem to find them from chip manufacturers. I'd love a hex buffer with complementary outputs that is in my logic family?

Thanks!

 

Do people mix and match logic families?

You can do it if you know what you're doing.

Second, what is a reasonable fanout for a buffered signal in this logic family? How can I get a larger fanout if needed.

The fan in/out characteristics will be described in the datasheet or a datasheet for the family. If you need a larger fanout, you'd use buffers/line drivers.

I'd love a hex buffer with complementary outputs that is in my logic family?

You're not going to find that in any logic family. The only logic family that routinely offered complementary outputs was ECL. MECL III was was the fastest logic family in the late 70's, operating at 300-500MHz. That was until HP Labs came up with some GaAs parts that ran at 1GHz+; though it wasn't widely available.

 

Not much call for discrete logic chips of any description these days. Your best bet is a suitably sized FPGA to go with the line drivers and receivers. It's cheaper and more flexible.

 

Not much call for discrete logic chips of any description these days. Your best bet is a suitably sized FPGA to go with the line drivers and receivers. It's cheaper and more flexible.

I identified FPGAs as good option for my project from the beginning, however, I have no experience or knowledge about them beyond what they are capable of. I’ve found very little beginner friendly information on them except to purchase a college textbook and a trainer board (expensive) and try to teach myself chapter by chapter (not that I am against doing so). I felt that discrete components were the path of least resistance to getting a working circuit.

Do you have anything that I could read up on that would help me understand how to select an FPGA for my application, program it, and integrate it into a PCB? I’m not afraid of diving into anything as long as I have a starting point.

My background is Mechanical Engineering (some Electrical with a focus in controls) and I do Industrial Automation design work.

 

I identified FPGAs as good option for my project from the beginning, however, I have no experience or knowledge about them beyond what they are capable of. I’ve found very little beginner friendly information on them except to purchase a college textbook and a trainer board (expensive) and try to teach myself chapter by chapter (not that I am against doing so). I felt that discrete components were the path of least resistance to getting a working circuit.

Do you have anything that I could read up on that would help me understand how to select an FPGA for my application, program it, and integrate it into a PCB? I’m not afraid of diving into anything as long as I have a starting point.

My background is Mechanical Engineering (some Electrical with a focus in controls) and I do Industrial Automation design work.

Everything I ever learned about new technologies from 1969 (graduation) to 2014 (retirement) came from materials provided by the manufacturer. We were so close to the bleeding edge that the textbooks had not yet been written. In college we still built tube circuits in case semiconductors were just a passing fad. For your first experience don't obsess about picking the optimum solution; that ability will come later. A wise mentor once told me that everything you design and build today will be in the landfill in ten years or so.

 

1) Define "fast". Propagation delay <1.4us is slooow. Fast is ns and ps.

2) Why do you think that you need complementary outputs? What is wrong with an inverter?

3) If you truly need fast and complementary then look at LVDS. Here we are talking GHz speeds.

 

1) Define "fast". Propagation delay <1.4us is slooow. Fast is ns and ps.

Total propagation through the circuit is what I was talking about, although I am sure my application is still, as you put it, sloooow

The signals will pass through a differential receiver, a shift register, perhaps 10-20 basic logic gates, a SR latch, another 5-10 logic gates, and finally a line driver. This all needs to happen before the next signal arrives (worst case 1.4us) with room to spare. The 74AC logic family looked to have propagation delays of 5-20ns per chip so there are no concerns, but the 7400 family was in the 200-300ns per chip so that probably wouldn't do.

2) Why do you think that you need complementary outputs? What is wrong with an inverter?

I plan on using both the signal and its complement in a decoder circuit. I will use an inverter, but didn't know if the signals arriving at slightly different times could cause problems.

I already had a part of my circuit checking for proper outputs of the input stage before enabling the decoder stage, so I can include the inverted signals in that as well.

I guess I am looking for a GO / NOGO on the use of 74AC logic family chips in my design. They seem pretty good to me, but I have a strong case of "I don't know what I don't know" going on and would prefer to be corrected now rather than after I finish the design and order PCBs.

Thanks so much for everyone's thoughts

 

Complimentary gates dont really exist "now days"
things like ECL used to "all" be complimentary outputs.

Re fan out. Rule of thumb. 10;1 . The original TTL chips were designed to drive 10 loads. so when other families have come out, they tend to be able to drive 10 loads, IN THE SAME FAMILY,. If you cross from one family to another, then things become more complex.

Also note, that original TTL 5v logic is all but dead. "all" logic now days is 3v3. Some 3v3 chips are capable of accepting 5v logic inputs. Even things like Arduino went 3v3 a good few years ago. I'd strongly suggest stay with 3v3 logic.

Differential outputs and inputs, tend to be "special" chips , depending what speed and distance you want to go over.
They range in speed / length / difficulty using from RS422 / RS485 chips, up through LVDS, through CML .


As for speed, just about the slowest TTL chips , have propagation delays of 10 ns, a lot faster than your talking.

Regarding FPGAs / CPLD's,
they are a lot more expensive start up than just a few logic chips, but the flexibility if thousand of times greater than logic chips. Look for 50 to 100 USD for a start up board,
select one that has a good forum, as you will be learning a new set of tools.

 

Modern chips use low voltage CMOS.

If you only need inverted signals because you are using combinational logic in a decoder you don't need complementary gates. Just use an inverter.

In any combinational logic decoder, expect to find glitches caused by "race" problems.
If your application cannot tolerate glitches then go to a synchronous design that employs clocked logic.

 

Andrew, Thanks for your response.

Re fan out. Rule of thumb. 10;1 . The original TTL chips were designed to drive 10 loads. so when other families have come out, they tend to be able to drive 10 loads, IN THE SAME FAMILY,. If you cross from one family to another, then things become more complex.

Sounds good. I can remember that. If I needed to go 20:1 or 30:1, would I put 2 or 3 buffers in parallel and do 10:1 on each of those? Or are there special buffers to drive 30:1 directly?

Also note, that original TTL 5v logic is all but dead. "all" logic now days is 3v3. Some 3v3 chips are capable of accepting 5v logic inputs. Even things like Arduino went 3v3 a good few years ago. I'd strongly suggest stay with 3v3 logic.

My input and output signals are 5V (can't change this due to the hardware I am interfacing with) as is my power supply. For simplicity I figured I'd stick with 5V CMOS rather than level shifting at each end and adding a voltage regulator. Maybe I am going about this incorrectly.

Differential outputs and inputs, tend to be "special" chips , depending what speed and distance you want to go over.
They range in speed / length / difficulty using from RS422 / RS485 chips, up through LVDS, through CML .

This is to interface with an encoder (discussed in detail in another thread). The input receiver is going to be the device that I am pretty sure TI recommended be used with the driver chip in the encoder. The output differential line driver will be the exact same chip as was in the encoder so I know it will work with the receiving device (servo drive).

Line Driver: AM26C31
Line Receiver: AM26LS32A AM26C32

they are a lot more expensive start up than just a few logic chips, but the flexibility if thousand of times greater than logic chips. Look for 50 to 100 USD for a start up board,
select one that has a good forum, as you will be learning a new set of tools.

I read through this article series https://numato.com/kb/learning-fpga-verilog-beginners-guide-part-1-introduction/ on FPGAs. I was a bit overwhelmed by the complexity they introduce. I have done lots of microcontroller work with pre-made boards, and some PCB design for basic slow speed peripherals, but have not ventured into putting a micro into my own design due to lack of knowledge of how to lay out peripherals, power supplies, programming interfaces, etc. I'm sure I could figure it out, but it just seemed more complex than I needed for this project. But maybe I am thinking about this the wrong way.

 

Modern chips use low voltage CMOS.

If you only need inverted signals because you are using combinational logic in a decoder you don't need complementary gates. Just use an inverter.

In any combinational logic decoder, expect to find glitches caused by "race" problems.
If your application cannot tolerate glitches then go to a synchronous design that employs clocked logic.

I am hoping to get around this by having an "inhibit" signal that is low until all the input conditions have settled and are static. Only then (when the Inhibit signal is high) are the input states evaluated by the decoder. As soon as new inputs arrive, the inhibit line drops low until the signals are finished being buffered by the shift register.

I think this is probably kind of like a clock signal, but I will be honest that I don't fully understand clocked logic. Been trying to read as much as I can find over the past few weeks when I started this project. It seems like clocked logic requires you to have exact control of when inputs are presented to your circuit which is not possible when those signals are coming from an external source that I have no control over.

 

Just a point,
AM26C31 is a RS 422 transceiver
also although it runs at 5v, you notice the logic thresholds on the TTL side are set to work with 3v3 or 5v logic.
,

 

Just a point,
AM26C31 is a RS 422 transceiver
also although it runs at 5v, you notice the logic thresholds on the TTL side are set to work with 3v3 or 5v logic.
,

So I am just starting to understand how logic families play together so bear with me if I make an error in this statement.

The "26" in the catalog number indicates TTL logic levels which are not directly compatible with 74AC CMOS technology.

The AM26C32 differential receiver is powered by 5V and should read the signals from the AM26C31 line driver in the encoder no problem. The logic high outputs of the AM26C32 receiver might be too low for the CD74AC164 shift register that they will be fed into. Assuming the AM26C32 does not have totem pole outputs (not sure how to find this out), a 10k ohm pullup resistor on the output wire to 5V should interface it to the CD74AC164 CMOS shift register without issue.

On the other end of the circuit, the inputs to the AM26C31 line driver will be driven by the output of 74AC logic gates. These should be completely compatible since the CMOS logic high level is plenty high for the TTL input of the AM26C31.

The RS422 outputs from the AM26C31 go into my servo drive where I assume they are compatible since the another encoder with the same output chip works fine with the drive.

Does all that sound correct?

 

I am hoping to get around this by having an "inhibit" signal that is low until all the input conditions have settled and are static. Only then (when the Inhibit signal is high) are the input states evaluated by the decoder. As soon as new inputs arrive, the inhibit line drops low until the signals are finished being buffered by the shift register.

I think this is probably kind of like a clock signal, but I will be honest that I don't fully understand clocked logic. Been trying to read as much as I can find over the past few weeks when I started this project. It seems like clocked logic requires you to have exact control of when inputs are presented to your circuit which is not possible when those signals are coming from an external source that I have no control over.

You'll want to inhibit not the signals coming into the decoder, but the signal coming out of the decoder. If you do it before the decoder, then as soon as you release the inhibit many signals into the decoder will be changing at the same time and they will not be changing at "exactly" the same time, so you will be subject to race-related glitches.

If you have asynchronous signals coming into a system the normal way of handling them is to double buffer them into the synchronous clocked domain. There are situations where this isn't suitable, but those situations often preclude the use of a clocked domain for processing those signals altogether and you should design a fully-asynchronous circuit -- and there be demons in those waters.

Ask yourself if several external signals change close to a clock edge whether it is critical that they all be recognized on the same clock period, or whether the system can be made to function properly if some of them are recognized on the current clock cycle and the others are recognized on the next.

 

You'll want to inhibit not the signals coming into the decoder, but the signal coming out of the decoder. If you do it before the decoder, then as soon as you release the inhibit many signals into the decoder will be changing at the same time and they will not be changing at "exactly" the same time, so you will be subject to race-related glitches.

That's exactly what I have planned on. There is one final AND gate at the output of the combinational logic decoder which requires the inhibit line to be high for the decoder signal to be output.

If you have asynchronous signals coming into a system the normal way of handling them is to double buffer them into the synchronous clocked domain. There are situations where this isn't suitable, but those situations often preclude the use of a clocked domain for processing those signals altogether and you should design a fully-asynchronous circuit -- and there be demons in those waters.

Again I feel like I am not understanding clocked circuits. It seems like you are saying that you collect the asynchronous signals and bring them into a clocked section of the circuit (unsure the exact implementation of the "double buffer").

Does "clocked" have to mean a fully free running clock (fixed frequency) or could it also apply to using some enable or inhibit line to trigger a single shot circuit execution?

I'm trying to stay away from the nitty gritty detils of my project (described here), but essentially I have an encoder signal coming in at a variable frequency (unable to know when the inputs will change). I only want my circuit to execute when there is a state change in the encoder. The information to be decoded from the signal requires my circuit to remember the last 3 states that the input has been in (sequential logic using a shift register) and taking the outputs of that to do combinational logic.

If I use a clocked shift register, the information shifts every clock cycle which isn't helpful to me (unless I'm missing something). The combinational logic only needs to evaluate the shift register outputs when there is a change, hence my preference towards asynchronous logic (but again, maybe I am missing something). Also I feel like I have not seen a "clocked" AND gate or similar logic gates.

Ask yourself if several external signals change close to a clock edge whether it is critical that they all be recognized on the same clock period, or whether the system can be made to function properly if some of them are recognized on the current clock cycle and the others are recognized on the next.

Going along with the above, it is important that the circuit recognize each input state change and none get missed or double counted. The information is contained in the relative timing of the 3 input signals, so if the state of the inputs were captured, but, for example, the 3rd signal missed the clock pulse somehow, then the circuit would produce an incorrect result.

 

So I am just starting to understand how logic families play together so bear with me if I make an error in this statement.

The "26" in the catalog number indicates TTL logic levels which are not directly compatible with 74AC CMOS technology.

The AM26C32 differential receiver is powered by 5V and should read the signals from the AM26C31 line driver in the encoder no problem. The logic high outputs of the AM26C32 receiver might be too low for the CD74AC164 shift register that they will be fed into. Assuming the AM26C32 does not have totem pole outputs (not sure how to find this out), a 10k ohm pullup resistor on the output wire to 5V should interface it to the CD74AC164 CMOS shift register without issue.

On the other end of the circuit, the inputs to the AM26C31 line driver will be driven by the output of 74AC logic gates. These should be completely compatible since the CMOS logic high level is plenty high for the TTL input of the AM26C31.

The RS422 outputs from the AM26C31 go into my servo drive where I assume they are compatible since the another encoder with the same output chip works fine with the drive.

Does all that sound correct?

part numbering,
take it all with big pinch of the Salts.
The AM26C32, , gets its number from the original AMD 2632 RS422 differential chips,
and why they were called 2632, who knows,

It used to be so simple in the 80's , with everything just 74TTL series, then came 74LS , 74ALS, 74HC et all..

What you need to do is look at the VoH and VoL for the driver chip, and ViH and ViL for the receiver at the drive current your expecting. If the driver can put the '1' signal in the window that the receiver wants for a '1' and the driver can put a '0' out in the window the receiver can accept as a low, then all is happy.