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Yes. That's why it's called a dominant pole capacitor. All the other poles are then moved to somewhere where the gain is already below unity, where they can't do any harm.
The other end goes to the OUTPUT not to GROUND.
Level shifting - transistor type selection
- Thread starter mondo90
- Start date
Yes sorry, it helped with bode plot gain - now it shows correctly ~17db:
However it is another feedback right? What is the mechanics of it, how does it help?
The current is 1/4th less without this cap. So the cap provides extra charge that was accumulated during positive swing? On the other hand why can't I just lower R3 value?
Look how the current changes as the waveform approaches the negative rail. Note that as the waveform approaches the negative rail, Q7 requires MORE base current to drive the load.
As the waveform approaches 0 the current follows and reduces from ~100mA to a ~5mA (no C2 connected). This is likely because the voltage goes down and so does the current. However the addition of C2 charges it during peak positive swing to a potential say ~3.5V so then, during negative swing, C2 shows -3.5V at the junction between R3 and R4 that serves as a current reservoir to account for missing dual power supply. Is my understanding correct?
Yes. correct. Not only have you produced a serviceable (it's not perfect) constant current source to drive the output stage, it has the ability to drive the base of the output transistor above the supply, which can get the output almost to the supply.
Thanks @Ian0. I have a few more questions:
1. In previous posts you said: "From an AC signal point of view, R2 and R13 are in parallel, so your gain should be 1+(R1/(R2||R13), which is 1+3000/500 which is 7. " It looks like you directly use the gain formula for Op amp, is that justified by the negative feedback?
2. The placement of C4 capacitor, why did you suggested it should be connected between a base and collector of Q5 and no other place?
3. This circuit finally works with single supply, however we saw that it is much easier to do it with double supply, therefore does it makes sense to first obtain dual supply (another circuit) and then proceed with op amp?
4. In order to provide a maximum power transfer the output resistance should match the load resistance, however here we have a significant mismatch, the output resistance of this amp is rather high: 3k+1k||1k ~=3.5K (skipping the C5 capacitance as it is of a very small resistance). Therefore should I add some small value resistance in parallel to C5 to bring it down?
1. In previous posts you said: "From an AC signal point of view, R2 and R13 are in parallel, so your gain should be 1+(R1/(R2||R13), which is 1+3000/500 which is 7. " It looks like you directly use the gain formula for Op amp, is that justified by the negative feedback?
2. The placement of C4 capacitor, why did you suggested it should be connected between a base and collector of Q5 and no other place?
3. This circuit finally works with single supply, however we saw that it is much easier to do it with double supply, therefore does it makes sense to first obtain dual supply (another circuit) and then proceed with op amp?
4. In order to provide a maximum power transfer the output resistance should match the load resistance, however here we have a significant mismatch, the output resistance of this amp is rather high: 3k+1k||1k ~=3.5K (skipping the C5 capacitance as it is of a very small resistance). Therefore should I add some small value resistance in parallel to C5 to bring it down?
Yes. You have just built an op-amp.
It also works connected between Q5 base and output. It gives a bigger reduction in output stage distortion, but if you have an output stage with a lot of phase shift it might not cure the instability.
It takes two extra resistors and an output capacitor. Fewer components than building the other half of the power supply, but having a ground that really is ground helps in some cases.
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The output impedance will already be incredibly low: the output resistance of Q6/Q7 divided by the excess gain. Impedance matching is not relevant here. If the output impedance is the same as the load impedance the maximum efficiency is 50%.
How did you determine that the output resistance is 3.5k?
The output impedance is much lower that that.
C5 and R12 constitute a high pass filter. If you want to pass frequencies above 20 Hz, you need C5 to be 1000 μF or (higher to go below 20 Hz).
I was working on a similar circuit, to get the output impedance, I plotted the ratio of the outputs of two identical circuits, one with 8Ω load and one unloaded.
The ratio of the two was 1.00097, that makes the output impedance, according to my calculations 0.00097*8Ω = 7.76mΩ, which is rather more the figure I would expect.
The problem is that it is testing it at quiescent conditions, with no signal output. The amplifier in question is seriously under biased so there is no real drive at that point, so a high output impedance.
I’d bet that if the amplifier output were forced into some DC offset where it is delivering power to the load LTS would get a very different result.
I just used the feedback loop as a main resistance, meaning 1k | 1k + 3k. But I think this is wrong, as I haven't taken the ro resistance of Q6 and Q7 into an account which will be in parallel to that right?
When you plot V_out/I_out then it takes the 8 ohm resistor load into an account right? Or what do you mean with no signal output?
Also, can you please provide some more context for what "underbiased" mean for you here?
As for my earlier question about the MAX power transfer, why do you say that it doesn't apply here?
Thanks
The output resistance is the open loop output resistance of the components multiplied by the open loop gain divided by the gain with feedback. The open loop output resistance is not easy to work out, but the output resistance is easy to measure.
It is the drop in voltage when a load is applied divided by the load current.
So, output voltage with no load MINUS output voltage with 8Ω load divided by the current through the load.
The SPICE method of injecting a signal into the output isn't particularly helpful as it only measures it at one voltage.
Underbiassed refers to the fact that there is no standing current through the output stage, so the Base voltage of the output transistors has to jump to +0.6V before any positive current can flow in the load, and the jump to -0.6V before any negative current flows. There is a dead band in the middle when no current flows.
@MrChips gave you an example of a biassed output stage in post #46
