Learning Verilog coding

Thread Starter


Joined Jan 26, 2010
My question is how do I know which inputs and outputs need to be
declared? In the example code intsig is not in the port list, why? Is this
because it is only used internal to the module, and if so no internal
ports need to be in the list as it is not a in or output to the module? It is declared in the code as: "reg out, intsig;"

I have included a module example.


module top_ver (q, p, r, out);

input q, p, r;
output out;
reg out, intsig;

bottom1 u1(.a(q), .b(p), .c(intsig));
bottom2 u2(.l(intsig), .m(r), .n(out));


Thread Starter


Joined Jan 26, 2010
Example: I have a module with a input to a flip flop called D1 (D1 listed in the ports list as input). If the output of the flip flop (Q1) is only used inside of the module will Q1 need to be in the port list or is it that in verilog only signals into and out of a module are considered a port and hence do not need to be listed?


Joined Dec 13, 2021
Not answering the question either

But a thought
why are you wanting to learn Verilog

If you like that language , and you have option, suggest that you learn System Verilog
Verilog has a good few "vague" bits,
reg / logic is one of the big ones that trips up people,
System Verilog, although you "can" write reg / logic ,
it encourages the use of a newer format,
that I see leads to a lot less problems,

Think of it as C++ compared to C,
you can write C in C++., but its not encouraged.

When you are certain,
get a book , one that teaches you
there are a few on line,
One tip,
to start with, once you have found a good book, stick to it
like all languages ,there are many variants on its usage
if you trawl net, and paste bits together, a newcomers are likely to now days
you end up more confused..
best to know a way well, rather than many ways badely,