In JK flip-flop, In all lectures I'm watching it says there is racing condition when clk, j and k are '1' and then Q becomes '0' when clk = '0' .Why is it so? When clock is' 0', Q can be' 1' or '0' depending on the previous state right?why is Q '0' when clock is '0'?

 

Your statement is taken out of context. Properly designed J-K flipflops do not behave like that.
You have to show us the circuit or a reference to where you saw this.

 

Master-slave JK flip flops don't behave like that but the four NAND gate version does.
See for instance: http://www.learnabout-electronics.org/Digital/dig54.php