Hi all,

The problem I have spent hours trying to resolve is the following: using JK flip flops build a pseudo random counter that counts 6,5,2,4,1,0,6.... I have attached my truth table, k-maps and Boolean simplifications to arrive with my Ta, Tb, and Tc inputs. I believe that my tables are correct but the counter is not functioning in multisim. What I feel that I am missing is a mechanism to cause the flip flops to "count" - i.e. it's acting as a stable circuit and not progressing through the count. Any feedback is very much appreciated!

 

I suggest you debug your understanding of the specific JK-FF part (SN74LS76D) by hooking the JK inputs of one part up to toggle on each clock pulse from your 75 Hz. source. Then try SET, CLEAR, and HOLD just to cement your understanding of the part.

TOGGLE is PRE=CLR=J=K=High. Output should toggle on positive clock edge.

Q: Does multisim require you to provide for power and ground to the chips?

The datasheet is here:
http://web.ece.ucdavis.edu/~bbaas/180a/Datasheets/sn74ls76.pdf

 

Several of your optimizations are sub-optimal. For instance, why can't Ka simply be tied HI?

Simplify your counter to a simple ripple counter or even just have each JKFF toggle independently to verify that your sim is at least alive.

 

I suggest you debug your understanding of the specific JK-FF part (SN74LS76D) by hooking the JK inputs of one part up to toggle on each clock pulse from your 75 Hz. source. Then try SET, CLEAR, and HOLD just to cement your understanding of the part.

TOGGLE is PRE=CLR=J=K=High. Output should toggle on positive clock edge.

Q: Does multisim require you to provide for power and ground to the chips?

The datasheet is here:
http://web.ece.ucdavis.edu/~bbaas/180a/Datasheets/sn74ls76.pdf

I suggest you debug your understanding of the specific JK-FF part (SN74LS76D) by hooking the JK inputs of one part up to toggle on each clock pulse from your 75 Hz. source. Then try SET, CLEAR, and HOLD just to cement your understanding of the part.

TOGGLE is PRE=CLR=J=K=High. Output should toggle on positive clock edge.

Q: Does multisim require you to provide for power and ground to the chips?

The datasheet is here:
http://web.ece.ucdavis.edu/~bbaas/180a/Datasheets/sn74ls76.pdf

A: Multisim does not require that you provide power or ground -which is a curse and a blessing. It also will does not require that you have appropriate resistance or cap values - so what works in the sim may just fry in the real world

 

Edit: this has to be a synchronous counter - so at the end of the day I have to trigger all clocks simultaneously.

 

If none of your FF outputs are beating up and down you may want to work out the problem in understanding (if that is what it is) by just getting one to beat up and down without any of it's inputs changing.

 

Edit: this has to be a synchronous counter - so at the end of the day I have to trigger all clocks simultaneously.

That's not really a big problem with a 75 Hz. clock. Your gate delays are on the order of tens of nanoseconds so you have more than enough setup time from one rising edge of the clock to the next.

 

Edit: this has to be a synchronous counter - so at the end of the day I have to trigger all clocks simultaneously.

That's fine and dandy, but don't worry about that yet. First determine that you can get the sim to work with a simple circuit. That way you can identify and fix any problems that aren't related to the logic of your counter but rather to how you are using the 7447 or the 7-seg display or the clock or some simulator setup parameter or even just how you are interpreting the sim results.

 

OK - I'm an idiot. Huge lesson learned though so thanks for the replies! Long story short - my K-maps were wrong because I did not fill the empty places with "X"'s. Once that was fixed the Boolean reduced correctly and I went from a rats nest to 1 - 1! - gate lol.

 

This also gives you some insight into how some problems are developed. A simple, essentially random, transition logic is made and then the behavior is checked to see if it makes a reasonable problem.