I am wondering what equation governs the operation of an n-channel JFET when V_ds is negative. All the resources I have found explain how it operates when V_ds is positive and V_gs is negative.

Id = k[2Vds*(Vgs-Vp)^2 - Vds^2] describes the current in the ohmic region.

The gate potential would still be less than the drain potential so the PN junction will still be reverse biased, drawing 0 steady-state current into the gate. Since the JFET is essentially a symmetrical device, I would guess that the equation would be the same as above but with Vsd instead of Vds and Vgd instead of Vgs:

Id = k[2Vsd*(Vgd-Vp)^2 - Vsd^2]

For anyone who is wondering, my intention is to create a circuit that will output an adjustable weighted average of several input voltages. My thought was to connect each input to the drain of a JFET. Then the sources would all be connected together as the output. The weights would be controlled by Vgs. However, since the sources will be a weighted average of the drains, some drain potentials will be below the source.


Thank you in advance for any help I can get. I appreciate it!

 

Controlling the weights by varying the Vgs is problematic, due to the high gain and non-linear Vgs versus drain current.
How will you know what the "weight" of each input is with that scheme?
How will you adjust the Vgs of each FET?

A more accurate and stable way to adjust the weight of each input is to run each through a multiplying D/A converter with the D/A digital word input controlling the weight.
All the D/A current outputs would connect to one opamp summing junction.

 

@crutschow thanks for the reply! I realize the gain would be high and Id would follow a quadratic curve against Vgs instead of a linear curve. I do not care about precision very much. The reason I wanted to use this method is to keep the component count and wire count as far down as possible.

My schematic so far for changing each Vgs is shown below. V1 is the supply voltage, and it is modulated to charge up the capacitor C2 through the transformer (inductive spiking may need to be snubbed). This will create a negative voltage relative to the common source of the JFETs. Then, activating the optocoupler U2 would charge C1 from C2, making Vgs more negative. Activating U1 would discharge C1, making Vgs less negative. Each JFET would have its own copy of C1, U1, and U2, but C2, V1, D1, L1, S1, and Q2 can be shared between all JFETs.

 

The reason I wanted to use this method is to keep the component count and wire count as far down as possible.

Well, that approach seems rather Rube Goldberg to me.
And I avoid the use of transformers wherever possible due to their cost and weight.

What is the nature of these input voltages that you want to "weigh" together?
There must be a better way to do it.

 

Fair dues, it does feel rather convoluted. The hard part is that none of the JFET terminals are referenced to anything at any given time. However, the transformer should not have to transfer more than a watt of power max.

This is meant to be for a sort of analog neural network. Never seen one, but I thought it would be something cool to experiment with. The drain voltages would be activations of the nodes in an input layer, and the source terminal would then be the activation of a neuron in the output layer. The Vgs voltages would be the weights. The output would be compared with the values from a training example, then put through a difference amplifier, then that would control the optocouplers to decrease the cost function by changing the weights. DACs would be used to constantly cycle training examples, but only on the first and last layer.

 

Okay, you lost me.
Good luck with that.

 

No worries, thanks for the help!!