I am wondering what equation governs the operation of an n-channel JFET when Vg is positive relative to the drain and/or source. I understand that if Vgs is positive but less than Vt, where Vt is the turn-on voltage of the PN junction, the depletion region will shrink, enhancing the channel as compared to when Vgs = 0. However, once Vgs = Vt, the depletion region is gone, and the channel can be enhanced no further. In this case, the gate will draw current. I understand that this is not what JFETs are normally used for, but I appreciate any help I can get. Thanks!
Since a JFET is symmetrical, Vgs and Vds can be interchangeable. What equations govern each current when Vd, Vs < Vg-Vt?
How about when Vs < Vg-Vt, but Vd > Vg-Vt?
Since a JFET is symmetrical, Vgs and Vds can be interchangeable. What equations govern each current when Vd, Vs < Vg-Vt?
How about when Vs < Vg-Vt, but Vd > Vg-Vt?