So I have a PSU that tracks well 1mV at a time (for low currents anyways, never needed high currents yet with this), and I have a brand new 6.5D DMM (Siglent SDM3065X)

I'm checking some JFET's I desoldered, from my broken Keithley 197 high impedance section, that deals in uA (they seem fine, there's only a broken relay so far). I'm plotting their curves in a database, by applying Vdd, through the DMM-DCI , into the drain, and measuring Ids. I'm wondering about the best way to zero this, and what's really zero ?.

The curcuit is:
PSU GND on source
PSU ch1->DMM(+)amps->DMMcom->JFET drain
PSU ch2 as the negative rail->JFET gate

With the COM of the DMM not attached to the drain, the DMM reads a +/-few nA, and REL-mode is off.

Once I plug COM of the DMM into the drain, with both PSU channels off, I get about -12.3uA (same after 20min), so a leakage out of the drain, back into the working DMM.

So when I'm trying to find the Gate pinch-off voltage, since around a 1uA might be entering the JFET (in the broken Keithley DMM), I really want to know the actual pinch-off and leakage current.

So with the Vdd and Vgg off, and the DMM Rel-mode off, I had about -12.3uA.
With the PSU at 15Vds, -1.95Vgs, I had +13nanoA after 125 averages @100PLC (not uA like above)

But if I turn off the PSU again, it drifts back to -12uA Ids, and then I zero it, and turn it back on, I have +12uA at Vgs=-1.95V.

So what do people do ?

 

Are the Jfets N-channel or P-channel?
An N-channel Jfet is pinched off and conducts a very low drain-source current when its drain has a positive voltage and its gate has a negative pinch-off voltage. When the gate voltage is the same as the source voltage (0V) then the Jfet conducts its zero gate voltage drain-source current (Idss).