Hello all,

I am designing a 6-layer mixed-signal board, where I have two 8-CH ADC, MCU, and punch of other digital circuitry.
In the ADC reference design, they used split ground planes and I have been reading that this technique is outdated and actually creates more SI problems
not to mention the difficulty to implement the split ground.

My question is, do I just use a single uninterrupted ground plane or follow the reference design and use a similar split ground plane approach? And if I used it, do I use it only on a single layer or all ground layers? knowing that I am using the following layer stack-up (Top: sig/pwr | In1: gnd | In2: sig/pwr | In3: gnd | In4: sig/pwr | Bot: gnd )

Thank you guys,

 

Hi,
It is outdated in my opinion. The opinion is based on talks from rick hartley, zach peterson and others
If you want to use it you have to split ground (and pwr) on all layers.

 

Hi,
It is outdated in my opinion. The opinion is based on talks from rick hartley, zach peterson and others
If you want to use it you have to split ground (and pwr) on all layers.

The thing is that I am routing power with signals.. so i will make a power fil for each power rail in each signal layer, do you think this is a good idea!?
and also in that reference design, they only split the ground adjacent to the ADC signals !? the left the other plane .

 

I think it depends a lot on your project. How many power rails do you have? Are the ADC and digital parts seperated. Do you need a pour next to the ADC input lines.
Is it possibly to use a stack like that:
Top: Sig
In1: GND
in2: Sig
In3: Sig
In4: PWR
Bot: Sig

Or

Top: Sig
In1: GND
in2: PWR
In3: PWR
In4: GND
Bot: Sig

 

No matter what you do, someone will say you should have done it differently. lol
Each design is different.
My thought is you have two choices. Either be smart with your grounds or be strong. (strong = solid ground(s) maybe more than one layer) Smart = study current flow and think "star".
Remember copper is free. Use as much as you can. Fill in any open area with ground.
I connect the bypass capacitors back to the IC's ground pin on the top side. This keeps that high frequency current off the ground plane.
I use many vias to connect the grounds together.

 

I think it depends a lot on your project. How many power rails do you have? Are the ADC and digital parts seperated. Do you need a pour next to the ADC input lines.
Is it possibly to use a stack like that:
Top: Sig
In1: GND
in2: Sig
In3: Sig
In4: PWR
Bot: Sig

Or

Top: Sig
In1: GND
in2: PWR
In3: PWR
In4: GND
Bot: Sig

I have 3 power rails 15V, 5V, and 3.3V so I will make a power pour for each one in a separate layer and connect to parts using vias as close to pins as possible.
I placed the analog parts as far as possible from any digital circuitry maybe as far as a centimeter or 2.
I don't think the stack-up you suggested will work for me, the first one has 2 signal layers adjacent to each other which is advised to avoid I think ! and also a signal layer is better to have a ground layer adjacent to it for better current return paths!
the second one has only 2 signal layers which aren't enough for me.

 

No matter what you do, someone will say you should have done it differently. lol
Each design is different.
My thought is you have two choices. Either be smart with your grounds or be strong. (strong = solid ground(s) maybe more than one layer) Smart = study current flow and think "star".
Remember copper is free. Use as much as you can. Fill in any open area with ground.
I connect the bypass capacitors back to the IC's ground pin on the top side. This keeps that high frequency current off the ground plane.
I use many vias to connect the grounds together.

I kinda expected that lol.
Thanks for the advice

 

I have 3 power rails 15V, 5V, and 3.3V so I will make a power pour for each one in a separate layer and connect to parts using vias as close to pins as possible.
I placed the analog parts as far as possible from any digital circuitry maybe as far as a centimeter or 2.
I don't think the stack-up you suggested will work for me, the first one has 2 signal layers adjacent to each other which is advised to avoid I think ! and also a signal layer is better to have a ground layer adjacent to it for better current return paths!
the second one has only 2 signal layers which aren't enough for me.

For high frequencies PWR and GND can be the return path ( because of the capacitance between both). Thats why stack 1 can work.


Another suggestion:
Top: Sig
In1: GND
in2: Sig/PWR
In3: Sig/PWR
In4: GND
Bot: Sig/PWR

You don't need ground between Sig on In2 and In3 because they have a return path on In1 and In4.
In this stack i would route the analog part on TOP

 

Here is an article about 6-Layer PCBs
https://resources.altium.com/p/6-layer-pcb-design-guidelines-pcb-design

 

For high frequencies PWR and GND can be the return path ( because of the capacitance between both). Thats why stack 1 can work.


Another suggestion:
Top: Sig
In1: GND
in2: Sig/PWR
In3: Sig/PWR
In4: GND
Bot: Sig/PWR

You don't need ground between Sig on In2 and In3 because they have a return path on In1 and In4.
In this stack i would route the analog part on TOP

Thanks for the suggestions,
I did put all analog section components on a single side, as tight as possible, and made sure not to route any tracks below it.

 

Thanks for the suggestions,
I did put all analog section components on a single side, as tight as possible, and made sure not to route any tracks below it.

I have seen designs that follow every "rule" and fail, and designs that ignore every Rule" and pass,

But I have seen plenty more that follow the rules and pass, and those that ignore the rules and fail.

the cost of 8 layers over 6 is all but zero compared to the costs of your time,
its only if your making thousands that layer reduction is worth while.

I have found this site of great use
https://learnemc.com/emc-design-guidelines