I was looking at PCI Express® Base Specification Revision 3.0 where I failed to find the details about DMA transaction support in PCIe protocol. Is it something that I can expect to appear in the specification document? If so, can anyone please point me out where to look at?

 

No, The DMA master is on the device(s) on the card. The device itself will master the bus and DMA from/to the PC memory. PCIe is a point to point protocol like networking.

 

No, The DMA master is on the device on the card. The device itself will master the bus and DMA from/to the PC memory.

Reading the Linux kernel PCI documentation, it seems DMA is an integrated part of PCI bus system.

Once the driver knows about a PCI device and takes ownership, the
driver generally needs to perform the following initialization:

Enable the device
Request MMIO/IOP resources
Set the DMA mask size (for both coherent and streaming DMA)
Allocate and initialize shared control data (pci_allocate_coherent())
Access device configuration space (if needed)
Register IRQ handler (request_irq())
Initialize non-PCI (i.e. LAN/SCSI/etc parts of the chip)
Enable DMA/processing engines

If DMA is not a part of PCIe specification, does the specification mandate every device supporting PCI should be able to act as a bus master?

 

Reading the Linux kernel PCI documentation, it seems DMA is an integrated part of PCI bus system.



If DMA is not a part of PCIe specification, does the specification mandate every device supporting PCI should be able to act as a bus master?

Sure there is a legacy DMA controller for the PCI bus. I don't think it mandates DMA for PCIe transfers but most do.
http://xillybus.com/tutorials/pci-express-tlp-pcie-primer-tutorial-guide-1

 

Sure there is a legacy DMA controller for the PCI bus. I don't think it mandates DMA for PCIe transfers but most do.

Does it mean PCIe devices can participate in non-DMA transfer, too? I was under the impression that only DMA transfer is possible for PCIe devices. I am pretty new to this domain, trying to develop some idea by reading disparate documents. Let me quote one such reading. The PCIe DMA section states that,

PCIe operates using a different paradigm. Instead of communicating with the host using a communication protocol, PCIe allows peripherals to gain Direct Memory Access (DMA) to the host’s memory. Using DMA, peripherals may autonomously prepare data structures within the host’s memory, only signalling the host (via a Message Signalled Interrupt) once there’s processing to be done. Operating in this manner allows the host to conserve computing resources, as opposed to protocols that require processing to transfer data between endpoints or to handle each individual request.

 

Does it mean PCIe devices can participate in non-DMA transfer, too? I was under the impression that only DMA transfer is possible for PCIe devices. I am pretty new to this domain, trying to develop some idea by reading disparate documents. Let me quote one such reading. The PCIe DMA section states that,

I haven't read every detail but usually in a specification when the word 'may' is used there are alternatives like legacy PIO modes. It's up to the device on the PCIe to configure I/O for the driver.

This looks like a simple PIO example for the Spartan.
https://www.intel.com/content/dam/w...ides/atom-xilinx-spartan-6-pcie-i-o-guide.pdf

Show a simple, register-mapped I/O adaptation based on the Xilinx Programmed I/O (PIO) design.