interval dependent one shot pulse length

Discussion in 'Analog & Mixed-Signal Design' started by patpin, Jun 10, 2018.

  1. patpin

    Thread Starter Active Member

    Sep 15, 2012
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    Is there a simple way to make a triggerable one shot which's square wave length depends on the interval between two other pulses?
    Lets assume that there is a pulse signal, I call it P, with a varying interval from 1.6mS to 54 mS.
    I would like to make a one shot firing at each pulse P (eg P at timePn and timePn+1) and producing a square wave of the length of the interval between tPn and tPn+1, substracted by e.g. 1mSec.
    E.g. if the interval was 30mS then the square wave should be 29mS. If there is a time needed for the calculation then this time should be substracted from the 1mSThis should be realised without using a microprocessor.
    The square wave length should be tPn+1 - tPn - (1mS-calculation time).
    If possible the 1mS should be slightly adjustable.
     
    Last edited: Jun 10, 2018
  2. Hymie

    Member

    Mar 30, 2018
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    There is if the square wave output starts at the end of the first pulse – but if you want the square wave to start at the end of the second pulse, that might be a bit trickier.
     
  3. WBahn

    Moderator

    Mar 31, 2012
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    Let's make sure I'm understanding what you are asking for.

    Let's say that you have a pulse at t = 2 ms and the second pulse is at t = 32 ms.

    Are you saying that you want the one shot pulse to go HI at t = 2 ms and return LO at t = 31 ms?

    If that's not what you are asking for, then when should the one shot go HI and return LO?

    It would be even better to sketch a timing diagram for at least three or four pulses indicating the one shot start/stop times relative to those pulses.
     
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  4. ebp

    Well-Known Member

    Feb 8, 2018
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    First, you have a huge problem if it is possible for a new initiating event for a pulse arrives before the previous pulse is finished. The times specified suggest that there could be a need to pipeline numerous pulses. If the total mark-space period is fixed, this is not an issue (i.e. under no circumstances can a new trigger arrive less than 54 ms after the previous one).

    Use the input signal to gate a very stable voltage into an integrator. Hold the integrated value (voltage) at the end of the pulse. Generate a new pulse using exactly the same method, ending the pulse when its integral is exactly equal to the held voltage, but don't generate the output until 1 ms after the start of the integrating interval - that is, delay the leading edge. If you have to delay the trailing edge you have a problem. You could easily make the output pulse a fixed fraction of the original, but clipping a millisecond off the end requires looking into the future. [EDIT - could also just de-integrate with the same integrator, ending the new pulse when the integrator returns to zero - very like the operation of a dual-slope analog to digital converter]

    [EDIT 2] - it should be possible to de-integrate a milliseond's worth of charge from the integrator capacitor, provided the voltage used for integration is well-regulated and not just stable and the integrator cap is stable (a requirement in any case). This would effectively take the millisecond off of the end of the pulse. The millisecond would be readily trimmable and in fact would probably require trimming because of capacitor initial tolerance.

    Though I used to take great delight in using analog methods because I could and the digital boys couldn't, just to annoy them, this is a job for a microcontroller. The program required is trivial and a processor with minimal pin count will do the job - you really only need 2 I/O pins, 2 for a crystal if you need the best timing accuracy and 2 for power. Analog circuitry would need to be carefully done for good accuracy and would be moderately complex.
     
    Last edited: Jun 10, 2018
  5. danadak

    Well-Known Member

    Mar 10, 2018
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    What is the latency allowed from time interval pulse is completed to generation of square wave
    pulse ?

    Regards, Dana.
     
  6. patpin

    Thread Starter Active Member

    Sep 15, 2012
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    I' ll try to answer a part of yr questions. The variation of the interval is rather slow. Lets assume that it takes 3-4 seconds to gradually go from an interval of 1.6mS to one of 54mS or back from there to 1.6mS. Since the sq.wave pulse length is always 1mS shorter than the interval there cannot be an overlap. The square wave (one shot) should be generated at each of the P pulses taking into account the previous interval.
    The latency for the generation can be up to 1mS but fixed.
     
    Last edited: Jun 11, 2018
  7. danadak

    Well-Known Member

    Mar 10, 2018
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    Seems like a simple time interval measurement between the pulses used
    to set a one shot PWM to generate the single square wave pulse.

    This should be straightforward in a PSOC. Several ways to do this -

    1) Counter to gen measure the incoming period. Then update PWM period/compare
    operated in single shot mode. Combo HW and SW.

    2) Verilog implementation in PSOC. HW only.

    3) Use state machine/LUT wizard in PSOC to do the incoming measurement
    then update single shot PWM. HW only.

    The incoming measurement implemented as reciprocal freq cntr.

    PSOC could also do a DDS approach vs PWM, but I do not see any advantage
    to doing this.

    Lastly PSOC could gen a sine or tri or custom waveform using its internal WAVEDAC
    component if you needed that additionally as output.

    [​IMG]

    Regards, Dana.
     
    Last edited: Jun 11, 2018
  8. patpin

    Thread Starter Active Member

    Sep 15, 2012
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    Thanks for suggestions. I'll be back after studying the possibilities you mentioned!
     
  9. Alec_t

    AAC Fanatic!

    Sep 17, 2013
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    The pulse period range you specify is in the same ball-park as vehicle tacho pulses. Is this the application?
     
  10. danadak

    Well-Known Member

    Mar 10, 2018
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    Something like This -

    upload_2018-6-11_6-30-45.png

    Timing resolution set to 1 uS. Could be much lower if needed.

    PWM operated in one shot mode, eg, gen just one square cycle on trigger

    Regards, Dana.
     
    Last edited: Jun 11, 2018
  11. WBahn

    Moderator

    Mar 31, 2012
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    The TS specifically excluded microprocessor-based solutions.
     
  12. patpin

    Thread Starter Active Member

    Sep 15, 2012
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    It is for an ignition indeed.
     
  13. patpin

    Thread Starter Active Member

    Sep 15, 2012
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    Hello , I call the pulse at 2 and 32mS the P pulse. The moment the one shot pulse goes high is not important as long as the latency is not > eg. 200µS. When it goes back down is important! and it should be at 29mS after the last P pulse in your example.
     
  14. WBahn

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    Mar 31, 2012
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    What is the tolerance on that 29 ms, or more properly, that 1 ms specification? Would 1.1 ms be okay? Would 1.01 ms unacceptable?

    Oh, and note that the abbreviation for milliseconds is ms, not mS -- the latter is the abbreviation for milliseimens, which is the amount of conductance of a 1 killohm resistor.
     
  15. danadak

    Well-Known Member

    Mar 10, 2018
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    PSOC using just its logic fabric capability with Verilog solution is not classified
    as a micro per se, more a small FPGA, just a collection of gates and flops and
    imagination. One can always waste the other 95% of its capability.

    Regards, Dana.
     
  16. patpin

    Thread Starter Active Member

    Sep 15, 2012
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    Thanks for the advise. 10% tolerance is OK.
     
  17. patpin

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    I presume processor speed is not a problem with this FPGA. You have an idea of price and learning curve?
     
  18. Alec_t

    AAC Fanatic!

    Sep 17, 2013
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    Here's a circuit which should do the job. Latency is the same as the pulse gap, i.e. 1ms. Replace R5 with a 100k pot if you want the gap to be adjustable.
    PulseStretch.PNG
    V1 is the input pulse source. R1,D1 protect the circuit from excessive input pulse amplitude (given the automotive application). U1a just squares up the input pulses. Latch U1b gets set by the input pulse and reset 1ms later. R5,C3 set the pulse gap width. A regulated supply (e.g. 9V) is recommended for the circuit.
    Attached is the LTspice simulation .asc file if anyone wants to play.
    PulseStretchPlot.PNG
     
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  19. danadak

    Well-Known Member

    Mar 10, 2018
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    The solution in low end, PSOC 4 would be ~$2, the 5LP high end $ 4 - $ 10

    PSOC 4 ARM Core M0, 48 Mhz
    PSOC 5LP ARM Core M3, 80 Mhz

    Learning curve, have you used an IDE before ? C or Verilog ?

    Regards, Dana.
     
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  20. patpin

    Thread Starter Active Member

    Sep 15, 2012
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    schematically.
    pulse length= previous interval - calculation time-1ms; only the end of the one shot is important and should be adjustable (potmeter)
     
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