I'm making an arbitrary waveform generator using a RPi Pico with an 8-bit R2R ladder DAC circuit. I can output a new voltage from my DAC every clock cycle (using DMA and PIO), giving me a 125MHz sample rate, but I would like to go higher!

My Idea is to have a second R2R ladder and interleave the outputs of the two DACs to double my sample rate. To do this I would use two fast switching mosfets as a 2->1 mux, that switch in the middle of every clock cycle. My problem is that I don't know how I could delay switching until half way through the clock cycle.

Would this even work? How might I delay the switching?

 

The switch will tend to add switching spikes in the output waveform from the gate-drain capacitance.

 

I'm making an arbitrary waveform generator using a RPi Pico with an 8-bit R2R ladder DAC circuit. I can output a new voltage from my DAC every clock cycle (using DMA and PIO), giving me a 125MHz sample rate, but I would like to go higher!

My Idea is to have a second R2R ladder and interleave the outputs of the two DACs to double my sample rate. To do this I would use two fast switching mosfets as a 2->1 mux, that switch in the middle of every clock cycle. My problem is that I don't know how I could delay switching until half way through the clock cycle.

Would this even work? How might I delay the switching?

Hello there,

For very fast things like this the best way I think is to use a dual phase clock. That's the way i did it when i was designing a digital oscilloscope many years ago before they were popular and widely available. I had to interleave the RAM memory chips. That's the way some packaged logic chips do it also. That eliminates the need for an actual delay circuit.
I am not sure you can do it this way or not for your application so you may have to look into using ECL and/or very high-speed comparators.

 

A minor consideration is that since you will increase the bits of resolution of your DAC, you need to pay attention to the tolerance of the resistors in the R-2R DAC so that the output remains monotonic. I have seen (and been involved in) various schemes over the years to increase the resolution of high speed DACs and the solutions have never been trivial.

 

I'm making an arbitrary waveform generator using a RPi Pico with an 8-bit R2R ladder DAC circuit. I can output a new voltage from my DAC every clock cycle (using DMA and PIO), giving me a 125MHz sample rate, but I would like to go higher!

My Idea is to have a second R2R ladder and interleave the outputs of the two DACs to double my sample rate. To do this I would use two fast switching mosfets as a 2->1 mux, that switch in the middle of every clock cycle. My problem is that I don't know how I could delay switching until half way through the clock cycle.

Would this even work? How might I delay the switching?

Since every clock cycle has both a rising and falling edge, the simple (not necessarily the best, or even acceptable) solution is to simply use the clock as the select input for the MUX -- on the HI half of the clock cycle it will choose one DAC and on the LO half it will choose the other. If the clock is a solid 50% duty cycle, this could get you "good enough". You will need to consider setup and hold times carefully and you might use a PLL to generate a duplicate clock signal that is slightly advanced or retarded to avoid such issues.

 

Wouldn‘t summing the two outputs give the same effect without the switching noise?

 

Since every clock cycle has both a rising and falling edge, the simple (not necessarily the best, or even acceptable) solution is to simply use the clock as the select input for the MUX -- on the HI half of the clock cycle it will choose one DAC and on the LO half it will choose the other. If the clock is a solid 50% duty cycle, this could get you "good enough". You will need to consider setup and hold times carefully and you might use a PLL to generate a duplicate clock signal that is slightly advanced or retarded to avoid such issues.

Hello there,

That's about the size of it, in theory. The problem sneaks in when it comes to the implementation.

When we think about it, if we use the logic high portion of the clock to enable one unit then that means that if the other unit is the same make and model the other unit also has to be enabled with a logic high. This presents a problem. In many logic circuits we can just use an inverter, and then when we get a high on the input and enable unit #1 when the input goes low, we get a high on the output which disables unit #1 and enables unit #2. That seems well enough except when the switching speeds go up high. It is then that the propagation delay of the inverter starts to make a big difference.
What may work is to use a buffer and an inverter where the buffer and the inverter have the same or very close to the same propagation delays. In that case we do have to rely on the delays being the same and staying the same. This is where a two-phase clock comes in. A two-phase clock is designed to have both high periods be the same so that both units get the same high pulse period and there is no delay between the two and no overlap. This isn't normally done with an inverter and a buffer but in some cases that may work. Usually a two-phase clock is a special design though.

Of course you might be able to come up with another solution. The idea here though is the implementation is 99 percent of the whole ballgame, not the theory behind it because the theory is rudimentary as I am sure you know.

I don't think I am telling you anything you don't already know just thought I would mention it to bring to light the importance of having the clocks be nearly perfect in the implementation.

 

A minor consideration is that since you will increase the bits of resolution of your DAC, you need to pay attention to the tolerance of the resistors in the R-2R DAC so that the output remains monotonic. I have seen (and been involved in) various schemes over the years to increase the resolution of high speed DACs and the solutions have never been trivial.

Hi,

Yeah, unfortunately this is delicate design where several problems can creep in.
There are some implementations that simply attempt to increase the resolution rather than the speed and they seem to work, but how well they work is another matter.