Hello everybody!

I'm working on a 2-phase interleaved buck converter design. the duty cycle is 0.545 and switches frequency is 100kHz. I'm getting results which I didnt expect: the average inductor currents are not the same although their sum is ~3.8A which is the needed load current. their peak-to-peak is also the correct value as was designed (~0.192A, 10% of average current). The problem is that the capacitor current is wrong, thus the output voltage ripple is not as i designed it to be (0.6V, 2% of output voltage which is 30V)
I did the 180 degree phase shift by delaying one of the switch's control signal by half a period (switch S2, parameter TD).

I added images of the circuit and resulting inductor currents.

the weird thing is that if i make a delay of 1.5*period, the difference between the average inductor currents gets even bigger but still sums up to ~3.8A. is the problem is that i try to make a phase shift by delaying a signal? i dont know another way of creating a phase shift for a square wave source in pspice.

please help. THNX!

 

Hello there,

Try pulsing one switch at a duty cycle that is less than 50 percent, and the other switch at the same duty cycle but after the first half of the cycle.

For example, try turning on the first switch at 0us on to 4us, and the second switch at 5us on to 9us, so they are both on for 4us but within different halves of the cycle. See if the waveforms stabilize to similar values.

So all we are doing here is using the top half circuit within the 0 to 5us period, and the bottom half from 5us to 10us. We never turn them both on at the same time, as one half works for the first half of the total time period and the other half works for the second half of the time period. This would be true interlacing.

Also, depending on frequency you might have to have more capacitance on the output than that shown. 10uf would probably be a min value, or maybe even 100uf, something like that.

 

Hi!
I changed the duty cycle to be less than 0.5 so that the two parts of the converter will work seperately but still same result. I have read about the fact that the phases should not be conducting at the same time but the instructor's demands were Vi=55V and Vo=30V, thus giving D=Vo/Vi=0.545 > 0.5. maybe i should add another phase? or two?

I noticed that there were huge current spikes in the sbreak elements. so i played with their Ron and Roff parameters. only when i put Ron at around 100Ω, i got that the average currents in the inductors are the same but now the value itself is very small. so i decided to use a more realstice switch - mosfet IRF150. no spikes but again average currents differ. i increased the capacitor size but no help. i even put snubber circuits across the switches (R=1k, C=1n) but nothing changes.

I'm pretty frustrated

 

Hi,

The fact that you have 30v out and 55v in doesnt change the fact that the two do not turn on at the same time. The entire duty cycle is 30/55 but that means each HALF does only HALF of that, or 30/110 each. So that means a low duty cycle for each half. Keep in mind that the duty cycle for a buck that you normally calculate will be for the entire switch time period, Tp, so for two operating interlaced each one would do half, or looking at it another way, each one would do the full duty cycle where the time period is Tp/2. So instead of 0us to 4us and 5us to 9us, try 0us to 2us and 5us to 7us for example. You should be able to figure out the exact switch times now (these are just rough trial values).

Also, what kind of diodes are you using? You need to use Schottky diodes or fast recovery diodes otherwise you will see huge current spikes when the switches turn on while the diodes recover and that will drastically reduce efficiency making it unusable in real life. The reverse voltage ratings of the diodes needs to be appropriate also.

 

Using 30/110 duty cycle for each switch produces an output of 15 volts which is half of what it should be so maybe i misunderstood you or something. currently im using the dbreak model with parameter n=0.001 to approximate an ideal diode. the idea is to first design an ideal circuit and then add realistic components.

 

@StasKO
I suspect that the issue is about carefully setting the phase relationship between the switching controls at startup. I ran a simulation of your system using PSIM. I can arbitrarily adjust the phase relationship for each switch controller. All simulations based on a sampling interval of 100 nsec.
With each switch controller set at 0 degrees phase shift, I obtain equal individual currents of 1.9165 A for a load current of 3.833 A. Load voltage ripple was 2.588V on 30 V average. Dominant ripple component was at 100kHz with components at 200 kHz and 300 kHz, etc.
With one controller at 0 degrees and the other at 180 degrees I obtain 2.004 A and 1.829 A as the individual average currents for a total load current of 3.833 A. Load voltage ripple was 0.171 V on 30V average.
If I adjust one controller to have a phase angle of -97.5 degrees and the other to +82.5 degrees I obtain individual average currents of 1.9165 A and 1.9165 A with the same load current of 3.833 A. Load voltage ripple was 0.17 V. Dominant ripple component was at 200 kHz on 30V average with zero 100 kHz component. Only even harmonics were present in the spectrum.
So clearly the phase relationship between the switch controllers has a significant effect - particularly on the output voltage ripple and harmonic content. It appears you could even use a lower capacitance to meet your 2% ripple spec. I guess it now falls to you to resolve the matter on a good theoretical footing.
Another approach might also be to include feedback control of the switching rather than your existing open loop control. One would have to guarantee that the switches operate 180 degrees out of phase and that the feedback control comprises an inner loop to equalise the currents from each converter and an outer output voltage control loop. This would then also ensure that the initial transient control behaviour would establish the required steady state conditions - rather than having to "tweak" the initial phase difference offset by trial and error (as I did).

 

Using 30/110 duty cycle for each switch produces an output of 15 volts which is half of what it should be so maybe i misunderstood you or something. currently im using the dbreak model with parameter n=0.001 to approximate an ideal diode. the idea is to first design an ideal circuit and then add realistic components.

Hello again,


What i was saying was that each switch must switch for 50 percent or less of the entire cycle.

For example, if the entire cycle is 10us long, then switch 1 only can turn on from 0 to 5us and that's it. It can not turn on from 0 to 6us or from 0 to 5.1us for example, because 5us is the limit for THAT switch. The second switch must switch on between 5us and 10us, and no where else. it can not switch on at 4.9us for example, it must always wait until the 5us mark which is half way through the full cycle of 10us.

Consider this...if you had two switches and you turn one on and held it on from 0 to 5us and then turned off but then had the other switch turned on from 5us to 10us, you would get the full output. That is of course only if you have the inductors large enough and the output capacitor large enough.

To get 30v output from 55v the duty cycle is 30/55 for a regular buck circuit. With two phases however you should be able to get this down to 30/110 for each switch.
If you can not get this to work, then your inductors and/or output capacitor(s) are too small, or you dont have the right diodes, assuming of course that you have the switches set up to turn on and off at the right times. You should look at the output of each switch first to make sure you have them set up right. They should never turn on at the same time.

So in the end you probably have to increase the values of either the inductors or the output capacitors. If the output capacitor is less than 1uf it is much too small for example.

 

@MrAl
If you read my post you will note the concept as outlined by the TS works just fine - at least from the simulation perspective.
Unfortunately I don't follow your argument.
For instance how do you arrive at the notion of switching duty being limited to 50%?

 

Hi,

50 percent PER switch, so it could still do 100 percent. That's interleaved.

 

Hi MrAl

I think I (hopefully) understand your point that "interleaving" suggests that overlapping of switch "on" control intervals is somehow a contradiction. I don't see this as a problem.
You appear to argue that one could obtain the desired output voltage by setting the duty of each switch such that each half of the topology contributes half of the total output voltage. This is unlikely to work since the individual converter outputs are effectively combined in parallel. Consider the analogous case where two DC sources are connected in parallel to drive a common load, whilst sharing the current. If the common load voltage is 'X' volts, what output voltage must each DC source supply? Clearly not X/2 volts.

My perception is that the suggested switch control has some advantage. What switching strategy might be sufficiently advantageous that one would adopt it?
It seems to me from my 'observations' (see post #6) of the various simulations, that the advantage lies in minimising the output ripple present for a given set of circuit component values. The advantage gained would have to be substantial to merit this approach. Perhaps there may be some additional benefit in the reduced current loadings (stresses) on the switches, capacitors and inductors. However, I must admit to substantial skepticism on claims of such 'beneficial' outcomes having regard to the likely increase in complexity and associated cost.
EDIT:
But my skepticism might have to be assuaged considering the plethora of articles on the benefits of the concept. See for instance: http://www.eetimes.com/document.asp?doc_id=1273224
NB: I do note that your point regarding a typical interleaved maximum duty cycle of 50%, is consistent with the literature. However, the literature does allow for interleaved operation with duty cycles greater than 50% - as curious as that might seem. See this paper for instance: http://www.ti.com/lit/slup231
In any event @StasKO has probably found the answer and moved on. Nothing unusual in that I guess - however frustrating it proves to be.

 

Hey guys! I'm still here. good to see that i got people interested . well i havent solved the not-equal inductor current problem but i understand why it is happening:
since both branches are parallel and equal, the rate at which the average inductor currents are rising is the same. so by giving one branch a "headstart" (by delaying the second branch start of operation by half a period), the second branch's inductor current will always be behind with respect to the first, non-delayed branch. since transient phase will end when the sum of average inductor currents will be at about 3.8A, then it is gauranteed that the non-delayed branch will have slightly higher average inductor current.

I assume that a solution to this issue will be to use some phase controller rather than delaying a signal. @t_n_k you are right about using closed loop feedback control. this is actually the second part of the design. Unfortunately our instructor, as it seems, doesnt really understand what he is doing because there are no interleaved buck controllers which their input range goes up to 55V (or more), their output range goes up to 30V (or more) and they are non-synchronous (in synchronous topology the diode is paralleled with another transistor to lower its forward voltage drop and thus losses).

Even more, after reading quite a bit about the interleaved buck topology, it seems that the reason it was developed is to solve problems that arise due to low voltage conversion such as in computers where it is used to convert a 12V supply to about 1V required by the CPU, for example. also it is used to lower the capacitor current ripple (by inductors currents cancellation effect) and thus lowering the amount of voltage ripple. also this allows for small enough components to fit in PCB's (by effectively generating a frequency which is N*f where N is the number of parallel branches and f is the individual branch frequency).

so after searching for hours in the sites of the largest chip manufacturers (Texas Instruments, Fairchild etc etc) there is not one controller that will fit my desing beacuse this is not what this topology is built for. Actually i did find one controller that might work but it's in synchronous topolgy so i guess ill have to ask my instructor for clarifications about the design criteria.

anyway, thank you very much for your help. I'll update this thread if ill get stuck once again even though i hope not because we have to hand the design by thursday.