Integrated Low Side Driver for External H Bridge

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step1hen

Joined Mar 15, 2018
2
Interested in ideas about the following problem

Normally when I have designed an integrated gate driver I have been using a low voltage process for example 5v and I have been able to use a set of ratio'd invertors to drive the Power MOSFET from an internal LDO or Vcc directly. In latest design I have to provide 10v gate drive, I have access to an internal 10v LDO, however the process selection allows for a maximum of 5v Vgs across both the N and P FET's of the process, I am wondering if the ratio'd invertor scheme can still be used with some kind of gate clamping circuits or is there another standard approach to use for this issue.
The sw frequency of the DC DC is 600KHz on pulses range from ~50ns to 100ns. Let me know if any thought or more info required.
 
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