I am trying to get a K53 Kinetis Freescale microcontroller and an ADAS1000SDZ Analog Front End microcontroller to talk to each other. I have the setup for sending words done and I can see the TX FIFO correctly being updated with the words I must send to the AFE (slave) to set control registers in the AFE and to send commands to the AFE to send back data.
I am able to get some data received only in debug mode. When I run the program normally, I just get zeros.
Moreover, the data that I am receiving in debug mode is not correct. I know this because If I must read the data at an address 0x11, I should get a 32 bit word whos MS bytes should be 0x11. i.e, 0x11abcdefg. This is not happening, or is happening too sporadically to say that I've succeeded.
One issue I had initially was timining. I've configured the ADE to output data at 2kHz and I should be having a minimum SCLK (master clock) of 768kHz. I had it too high, initially, and was receiving no data at all. Having lowered the SCLK to about 1500 kHz, I am receiving this incorrect data.

I have attached my code for writing to registers and the initializations. Any suggestions would be much appreciated as I have spent quite a bit of time trying to get the correct data in, trying out different combinations of clock polarity and so.

My Initializations are like so:

      SPI0_MCR = ((SPI_MCR_HALT_MASK) | //halts transfers
                  (SPI_MCR_MDIS_MASK & 0x00)); //enables module clocks
      SPI0_MCR = (SPI_MCR_MSTR_MASK )| //master mode
                 (SPI_MCR_ROOE_MASK)| // incoming data shifted into shift register
                                      //overwriting previous data
                                      //when RX FIFO is full
                  (SPI_MCR_DCONF(0x00))| // SPI
                    (SPI_MCR_PCSIS(1))| // determines inactive state of PC(X):
                                         // 0 : inactive PC(x) is low
                      (SPI_MCR_DIS_TXF_MASK)|
                        (SPI_MCR_DIS_RXF_MASK)|
                          (SPI_MCR_CONT_SCKE_MASK && 0x00); //continuous SKE enable
                  

    SPI0_CTAR0 = (SPI_CTAR_DBR_MASK & 0x00) |
                (SPI_CTAR_FMSZ(0x07)) | //frame size = 8bits
                  (SPI_CTAR_PDT(0x00)) |
                    (SPI_CTAR_BR(0x04)) | //was 0x07  //baud rate prescaler
                      (SPI_CTAR_CPOL_MASK & 0x00) |
                        (SPI_CTAR_CPHA_MASK & 0x00) |
                          (SPI_CTAR_PBR(0x02)) | //was 0x02  /pre baud prescaler
                            (SPI_CTAR_PCSSCK(0x02) |
                             (SPI_CTAR_PASC(0x00)) |
                               (SPI_CTAR_CSSCK(0x06)) |
                                 (SPI_CTAR_ASC(0)) |
                                   (SPI_CTAR_PDT(0x00)) |
                                     (SPI_CTAR_DT(0))) ; // mode 0 operation
  
    SPI0_MCR &= 0xfffffffe ; //start transfers again

And the way I write to registers is byte by byte, so for 32 bit word I must push 4 times for one word.

int register_configure(int address)
{
     //int data[5];
     int data;
     unsigned int data1,data2,data3,data4;
     int address1, address2, address3,address4;
     address1 = address & 0x000000ff;
     address2=address & 0x0000ff00;
     address2 = address2>>8;
     address3 = address & 0x00ff0000;
     address3 = address3>>16;
     address4 = address & 0xff000000;
     address4 = address4>>24;
     address4 = address4 & 0x000000ff;
     SPI0_PUSHR = ((SPI_PUSHR_CTAS(0x00)) | //The CTAR0 is selected
                   (SPI_PUSHR_CONT_MASK) | //Chip select is continuous through transfers
                     SPI_PUSHR_TXDATA(address4))|
                       SPI_PUSHR_PCS(1) ; //Pushes the required data
                      
    
     while((SPI0_SR & SPI_SR_TCF_MASK)==0){}//wait till the transfer is complete
     data1 = SPI0_POPR; // the latest data in the RX FIFO is transferred to data1
     while((SPI0_SR & SPI_SR_TFFF_MASK)==0); //wait till the TX FIFO is not empty
     while((SPI0_SR & SPI_SR_RFDF_MASK)==0); //wait till the RX FIFO is not empty
    
    
     SPI0_SR |= SPI_SR_TFFF_MASK; // TX FIFO is not empty set
     SPI0_SR |= SPI_SR_RFDF_MASK; //sets the RX FIFO is not empty flag   
     SPI0_SR |= SPI_SR_TCF_MASK; //Transfer is complete flag set
    
     SPI0_PUSHR = (SPI_PUSHR_CTAS(0x00)) |
                   (SPI_PUSHR_CONT_MASK) |
                       SPI_PUSHR_TXDATA(address3)|
                          SPI_PUSHR_PCS(1); //CS is asserted
     while((SPI0_SR & SPI_SR_TCF_MASK)==0){}//wait till the transfer is complete
     while((SPI0_SR & SPI_SR_TFFF_MASK)==0); //wait till the TX FIFO is not empty
     while((SPI0_SR & SPI_SR_RFDF_MASK)==0); //wait till the RX FIFO is not empty
     data2 = SPI0_POPR; // the latest data in the RX FIFO is transferred to data1
  
  
     SPI0_SR |= SPI_SR_TFFF_MASK; // TX FIFO is not empty set
     SPI0_SR |= SPI_SR_RFDF_MASK; //sets the RX FIFO is not empty flag   
     SPI0_SR |= SPI_SR_RFOF_MASK;
     SPI0_SR |= SPI_SR_TCF_MASK; //Transfer is complete flag set
        
    
     SPI0_PUSHR = (SPI_PUSHR_CTAS(0x00)) |
                    (SPI_PUSHR_CONT_MASK) |
                      SPI_PUSHR_TXDATA(address2)|
                        SPI_PUSHR_PCS(1);
     while((SPI0_SR & SPI_SR_TCF_MASK)==0){}//wait till the transfer is complete
     while((SPI0_SR & SPI_SR_TFFF_MASK)==0); //wait till the TX FIFO is not empty
     while((SPI0_SR & SPI_SR_RFDF_MASK)==0); //wait till the RX FIFO is not empty
     data3 = SPI0_POPR; // the latest data in the RX FIFO is transferred to data1
  
  
     SPI0_SR |= SPI_SR_TFFF_MASK; // TX FIFO is not empty set
     SPI0_SR |= SPI_SR_RFDF_MASK; //sets the RX FIFO is not empty flag   
     SPI0_SR |= SPI_SR_RFOF_MASK;
     SPI0_SR |= SPI_SR_TCF_MASK; //Transfer is complete flag set
    
    
     SPI0_PUSHR = ((SPI_PUSHR_CTAS(0x00)) |
                   (SPI_PUSHR_CONT_MASK) |
                     SPI_PUSHR_TXDATA(address1)|
                       SPI_PUSHR_PCS(1));
     while((SPI0_SR & SPI_SR_TCF_MASK)==0){}//wait till the transfer is complete
     while((SPI0_SR & SPI_SR_TFFF_MASK)==0); //wait till the TX FIFO is not empty
     while((SPI0_SR & SPI_SR_RFDF_MASK)==0); //wait till the RX FIFO is not empty
     data4 = SPI0_POPR; // the latest data in the RX FIFO is transferred to data1
  
  
     SPI0_SR |= SPI_SR_TFFF_MASK; // TX FIFO is not empty set
     SPI0_SR |= SPI_SR_RFDF_MASK; //sets the RX FIFO is not empty flag   
    
     SPI0_SR |= SPI_SR_TCF_MASK; //Transfer is complete flag set
     data = (((data1<<24) & 0xff000000)|((data2<<16)&0x00ff0000)|((data3<<8)&0x0000ff00)|(data4 &  0x000000ff));
    
     return data;
}

Moderators note : Please use code tags for pieces of code

 

So after scoping out the SCLK, MISO, MOSI and CS, I have seen that the CS, MOSI and SCLK are actually as I expect them to be and they are going into the ADAS1000 (slave) correctly. However the ADAS1000 is giving out a signal on the MISO line that is very noisy. Since the commands sent were correct, I am unable to find the problem.

 

One thing might be to check what size int is for your compiler, it may not be a 32-bit number.

As far as the noise, are the grounds connected between the two? A schematic might help...

 

One thing might be to check what size int is for your compiler, it may not be a 32-bit number.

As far as the noise, are the grounds connected between the two? A schematic might help...

That was actually the whole problem. The grounds weren't connected, and the noise hence caused the garbage. I have never had to connect boards because they are usually connected to the PC, but this time the ADAS isn't connected to the PC. Thanks!