# Implementation of NAND gate

#### s3eng

Joined Oct 3, 2015
1
hey guys i dont understand how this implementation of nand gate works...
I can understand this, However i am having trouble understanding the logic behind the implementation of the NAND gate. According to the circuit on the left shouldnt
Y's output be 0 when A AND B is 0? I know for NAND gates 0 and 0 is 1. However i dont undestand how the circuit diagram on the left works (means not the truth table and the NAND gate diagram on top of the table). #### WBahn

Joined Mar 31, 2012
26,412
hey guys i dont understand how this implementation of nand gate works...
I can understand this, However i am having trouble understanding the logic behind the implementation of the NAND gate. According to the circuit on the left shouldnt
Y's output be 0 when A AND B is 0? I know for NAND gates 0 and 0 is 1. However i dont undestand how the circuit diagram on the left works (means not the truth table and the NAND gate diagram on top of the table). 