Sorry, but now you lost me, with don't care conditions it means that it can be a zero or a one and the output won't be affected right? I don't quite understand since the outputs differ quite a lot. From my understanding so far, if the truth table is correct then the circuit is working as it should. How does don't care conditions come into play here?

 

View attachment 223564
Here is the 8-1 mux. I got the circuit to work but not correctly... It only works when I connect Y' and E' to ground/power. Where should these pins be connected?

The E' is the "enable output" input and it is active LO, so that pin has to be held in a LO state in order to get any output.

The Y' is the inverted output and it should NOT be connected to anything. Tying it LO (or HI) could damage the chip.

In general, all inputs should be driven to a valid HI or LO input state, while unused outputs should be left floating.

Note that the same goes for your other chip. If you have six inverters and you are only using one of them, then you need to tie the inputs of the other five to valid logic levels. This is particularly important with CMOS logic families.

 

The E' is the "enable output" input and it is active LO, so that pin has to be held in a LO state in order to get any output.

The Y' is the inverted output and it should NOT be connected to anything. Tying it LO (or HI) could damage the chip.

In general, all inputs should be driven to a valid HI or LO input state, while unused outputs should be left floating.

Note that the same goes for your other chip. If you have six inverters and you are only using one of them, then you need to tie the inputs of the other five to valid logic levels. This is particularly important with CMOS logic families.

Okey, thank you! I did that and the truth table is still the same...can you perhaps explain what ericgibbs meant? Trying to grasp it...

 

hi 23,
The point I am raising is that the conditions for an Output can be realised in more than one unique combination of the Bit pattern

eg: consider /Q3 /Q2 /Q1 the Q0 bit state is not specified.

So in the binary count Up pattern

0000 will give a High Out
0001 will give a High Out

Also /Q3 _ /Q1 Q0 , Bit Q2 is not specified.

So
0001 = High out
0101 = High out.

There a other cases where a High will result from inputting a 4 Bit incrementing count, so don't expect to only see a High output for the above 6 equations. when using a 4 bit counter drive.

E

 

progress! thank you!, I changed so that the LSB is the one to be inverted and Q3, Q2, Q1 as select inputs. What a difference.

This video at around 8:20 explained a lot.
I understand now Eric, thank you, with the LSB as input it means that those don't care conditions do not arise? I am currently trying to figure out why I get 2 wrong outputs

 

hi 23.
Pleased to see that you are making progress, please post your circuit when ready, I will try a simulation run.
E
BTW: You must not create logic circuit that will give a High output for all combinations of a 4 Bit binary count, just the bit pattern that meets the criteria of the problem equations you have been given.

 

In the blue box where Y=0, I have connected input I3 to ground and where Y=1 I have connected it to power. I don't understand why connecting input 3 of the mux to ground won't give me the output 0. For input I5, it is a mystery aswell. Is it perhaps that every inverted Q0 needs an individual inverter? Right now I have only used 1 of the 6 inverters in the chip and simply taken the signal from from the same inverter so to speak.

 

hi 23.
Pleased to see that you are making progress, please post your circuit when ready, I will try a simulation run.
E
BTW: You must not create logic circuit that will give a High output for all combinations of a 4 Bit binary count, just the bit pattern that meets the criteria of the problem equations you have been given.

Ohh, so it should only cover the equations received from the minimization from the K-map? It does that quite well actually. But my teacher last time only cared if it fulfilled the truth table. So, if I can fix these two wrong outputs everything is golden.

 

this is the task we were given

 

Thank you everyone for all your help! The circuit is done and working perfectly. Learned a lot from your feedback. I will post a circuit diagram soon.

 

hi 23,
Pleased to hear all OK.
Looking forward to seeing your final work.
E

 

hi 23,
Pleased to hear all OK.
Looking forward to seeing your final work.
E

Like this but instead with a 8-to-1 mux, but Logisim seems not to allow 3 select inputs so I did it using only 2-to-1 mux.

Here it is in reality