About the third select input, should that one also be connected to ground in that case?

You can tie it either way; the choice merely dictates which set of four inputs are still accessible.

If you go that route, you still have to use additional gates to get the right logic from the other two inputs to the four active inputs of the MUX. Why do that, when you can use all three of the select inputs and use a single NOT gate to get whatever logic you need from the remaining input to each of the eight active inputs?

 

h23,
Just a quick small section, excuse messy drawing.
E
View attachment 223544

Good explanation, I understand now! Thanks

 

Good explanation, I understand now! Thanks

But you already had a shining example of that approach right in front of you. Look at the image you used in your initial post. Why were there only two inverters in that circuit and why were they used where they are and drawn the way they were drawn?

 

You can tie it either way; the choice merely dictates which set of four inputs are still accessible.

If you go that route, you still have to use additional gates to get the right logic from the other two inputs to the four active inputs of the MUX. Why do that, when you can use all three of the select inputs and use a single NOT gate to get whatever logic you need from the remaining input to each of the eight active inputs?

Damn, now you are talking. Makes everything a whole lot easier... For instance, I see that Q1 is in every term, that would be the one to pass through the NOT gate if needed and Q3, Q2, Q0 should be my select inputs in that case?

 

But you already had a shining example of that approach right in front of you. Look at the image you used in your initial post. Why were there only two inverters in that circuit and why were they used where they are and drawn the way they were drawn?

Indeed, got blinded by my own confusion.

 

Damn, now you are talking. Makes everything a whole lot easier... For instance, I see that Q1 is in every term, that would be the one to pass through the NOT gate if needed and Q3, Q2, Q0 should be my select inputs in that case?

You can pick any three inputs to be your select inputs and you can use them in any order. In SOME cases, judicious choice of the three select signals can remove the need for the inverter altogether, but that won't always be possible.

 

You can pick any three inputs to be your select inputs and you can use them in any order. In SOME cases, judicious choice of the three select signals can remove the need for the inverter altogether, but that won't always be possible.

Alright, time to dive in and try this out. Thank you for everything.

 

Indeed, got blinded by my own confusion.

You want to develop the habit to look at circuits and consider why they were done the way they were. That will help you build up a fuller bag of tricks that you can use. It is particularly valuable when you see circuits that are done in a way that doesn't make sense to you or that you think you see a "better" way to do it. While it is certainly possible that the person that did it did a non-optimal job, it is best to assume, at least initially, that they had a good reason for doing it they way they did. See if you can identify any advantages to their approach. Even if they did a poor job, you have the potential to learn to identify approaches that might be avoided so that you can recognize them when you go down the rabbit hole on your own designs later.

 

You want to develop the habit to look at circuits and consider why they were done the way they were. That will help you build up a fuller bag of tricks that you can use. It is particularly valuable when you see circuits that are done in a way that doesn't make sense to you or that you think you see a "better" way to do it. While it is certainly possible that the person that did it did a non-optimal job, it is best to assume, at least initially, that they had a good reason for doing it they way they did. See if you can identify any advantages to their approach. Even if they did a poor job, you have the potential to learn to identify approaches that might be avoided so that you can recognize them when you go down the rabbit hole on your own designs later.

Thank you for the advice, my professor said something very similar. I'm in the first year of electrical engineering so seeing patterns is just starting to form.

 

Thank you for the advice, my professor said something very similar. I'm in the first year of electrical engineering so seeing patterns is just starting to form.

It is a skill that requires practice and patience to get good at -- and no one is ever perfect at it or can't get better.

Remember that engineering is both an art and a science. The art is learning from your own mistakes. The science is learning from the mistakes of others.

 

Here is the 8-1 mux. I got the circuit to work but not correctly... It only works when I connect Y' and E' to ground/power. Where should these pins be connected?

 

hi,
This is the d/s for the 151.
E

 

hi,
This is the d/s for the 151.
E

I got this file given to me from class.
When I leave these pins, I receive no output, why is that? And when I connect them to ground or power I receive different truthtables.

 

hi,
Its as this image of the table.
/G must be at 0V to select the IC
Y is the True Ouput Levels
and
W is the Inverted
E

 

I'll just start over slowly. To explain what I have done:
Q3, Q2, Q0 are connected to the mux as select inputs. Then from the K-map I got:


wherever there is Q1' I connected that to the inverter and then to one of the mux-inputs (have 4 inverted Q1). Then non-inverted Q1's are connected directly to the mux inputs. The mux-inputs not used (I0 and I1) are connected to ground. Then from the mux, the output Y is connected to a LED that should shine when the truthtable shows 1 for the given inputs. What am I missing?

 

Hi,
Any chance of a simple sketch, it will be easier to follow.
E

 

Like this. Got a family gathering going on so might not answer until a few hours. I don't really know what I'm doing wrong given the advice I got from everyone here.

 

hi,
This is a LTS sim of your circuit. [check it for accuracy].
You can check the operation by inspecting the 5 plots, which are in time sync.
Ignore the spikes, just a ripple counter drive.
E

 

Tried the way you showed and this is what I get... It works but I don't get the right truth table. The first gate (the one closest to the pushbuttons) is a NOT-gate and the second is the mux. I thank you for your patience with me.

 

hi,
Remember you have some don't care states in the 6 equations. containing only 3 active Bits, in a 4 bit Word.
Compare the equations with the mapping, the don't cares can be any state!
E