I'm trying to understand I2C communication protocol and I've been reading a lot of material. To be honest, I think I don't have enough knowledge to understand this protocol.

I'm having trouble understanding the concept of a clock signal in communication. I don't understand clock stretching ?

I know that the crystal oscillator in the microcontroller generates a square wave, which we call clock signal. clock signal can be either high or low.

 

Clock stretching is a way for the slave to throttle the clock if it is having trouble with the speed being set by the master. The slave can (within limits) hold down the clock line to stretch the pulse in order to have sufficient time to respond.

So, it’s like the slave is grabbing the second hand on a clock to make the seconds slower so it has “more time” since the master thinks that time is only what the clock says it is. By stretching the seconds of the clock, the slave makes the master “run in slow motion” so it can catch up.

The limits on clock stretching are in high speed mode where it is only allowed between the ACK bit and the first bit of the next byte, exclusively and it is prohibited between bits 2 and 9 because the protocol has the edges of those bits boosted from a separate current source.

 

hi Kitt,
This I2C PDF explains the signals.
E

 

For first time user of I2C, you can ignore the MCU crystal oscillator frequency. The master MCU can send I2C SCL at whatever the program chooses.

Also ignore clock stretching for now. Just send SCL at a slow enough speed for the receiver to handle.

 

The master MCU can send I2C SCL at whatever the program chooses.

I want to understand the meaning of above line.

As far as I can understand master is a device which is sending square wave to slave device. Slave device will receive signal from master device

 

You raise and lower the clock signal for each bit of data you send. It s not a continuous clock from an oscillator. I just tells the device that data is available.

 

I want to understand the meaning of above line.

As far as I can understand master is a device which is sending square wave to slave device. Slave device will receive signal from master device

The master sends SCL which has a leading edge and a trailing edge.
The time duration between the two edges is under control of the programmer. You can choose whatever time you want.

 

Master can transfer bit on the rising edge of the waveform or the falling edge.

Slave can receive bit on the rising edge of the waveform or the falling edge.

Let's say the master transfer bit on the rising edge of the waveform. on which edge the slave will receive the bit ? rising edge or falling edge?

In a case I think the master will transmits a bit at rising and the slave will receives a bit falling edge. but I really don't know if that is correct.

 

Master sends SDA signal (blue).
Master sends SCL rising edge.
Slave monitors SCL rising edge.
Slave strobes SDA signal (green).

Reference: https://en.wikipedia.org/wiki/I²C

 

View attachment 284873

Reference: https://en.wikipedia.org/wiki/I²C

This is a basic picture diagram that I have drawn to understand I2C write operation


doubts

SDA goes low or high at 9th clock, who set value of SDA, Master or Slave ?

I think slave set 5v on SDA pin if it's not acknowledge byte and 0V if slave acknowledge

 

SCL and SDA are open drain outputs. This means that there are pull-up resistors that will set SCL and SDA high when there is no active signal.

In bus systems, this implements a logic OR function for ACTIVE-LOW logic, i.e. /A OR /B.
Master or slave can set the signal LOW. Neither master nor slave need to set a signal HIGH. This is already accomplished by the pull-up resistor.

The receiving slave device sends ACK by holding SDA low on the 9th SCL period.

 

I'm big confused with I2C read transaction. Can someone explain what the I2C standard says about the read operation?

Transaction to read I2C Device

1. Master send address of slave plus read bit.
2. Slave generate ACK/NACK signals
3. If master received NACK. Master generate stop conditions.
4. If master received ACK, what next

Does the master send the address of the register to slave device in read transaction or write transaction?

 

Master sends the address as a "write". Then the whole process stops and starts again as a read.
There is a condition called "repeated start" which can be used between the two to hurry things up.
[Edit] There a possibility for confusion here. For I2C memories, the master has to send the memory address from which the data is to be read.
That is different from the master sending the I2C address from which data is to be read.

 

I'm big confused with I2C read transaction. Can someone explain what the I2C standard says about the read operation?

Transaction to read I2C Device

1. Master send address of slave plus read bit.
2. Slave generate ACK/NACK signals
3. If master received NACK. Master generate stop conditions.
4. If master received ACK, what next

Does the master send the address of the register to slave device in read transaction or write transaction?

The master sends the Address in ALL transactions.
What next is that after the ACK you send 8 more clocks to read the data and during that time, your SDA output on the master must be high so that the peripheral device can "drive" the SDA line low.

 

Master sends the address as a "write".

The slave device has an address and also a register address in which the data is stored.

Then the whole process stops and starts again as a read.
There is a condition called "repeated start" which can be used between the two to hurry things up.

Assuming that the data has been stored on the internal registers of salve in the write operation.

How do we know on which register we want to read store data in read operation?

Edit : 1
Transaction to write data to slave device .

1. Master generate start condition.
2. Master send address of slave device plus write bit on bus
3. Slave generate ACK/NACK signals
4. If master received NACK. Master generate stop conditions.
5. If master received ACK, Master send next byte, Adress of internal register to slave device.
6. Slave generate ACK/NACK signals.
7. If master received NACK. Master generate stop conditions.
8. If master received ACK, Master send next byte to location of internal register..
9. Master generate stop condition

Edit 2
Transaction to read I2C Device

1. Master send address of slave plus read bit.
2. Slave generate ACK/NACK signals
3. If master received NACK. Master generate stop conditions.
4. If master received ACK, what next

 

[Edit] There a possibility for confusion here. For I2C memories, the master has to send the memory address from which the data is to be read.

@Ian0

In which transition it happens in read or white transition?
please take look at sequence I have post in #16

 

@Ian0

In which transition it happens in read or white transition?
please take look at sequence I have post in #16

What type of I2C device are you using? Is it a memory?

 

What type of I2C device are you using? Is it a memory?

I am not using any specific device but I am reading data sheet for MCP23017

Page 14 I2C read operation.

https://ww1.microchip.com/downloads/en/devicedoc/20001952c.pdf

 

I'm trying to understand I2C communication protocol and I've been reading a lot of material. To be honest, I think I don't have enough knowledge to understand this protocol.

I'm having trouble understanding the concept of a clock signal in communication. I don't understand clock stretching ?

I know that the crystal oscillator in the microcontroller generates a square wave, which we call clock signal. clock signal can be either high or low.

What is a clock? A clock is something that keeps time. In digital systems, a 'clock' represents a state of change in a time stream. The only way to know that something has happened is to change it's state. The only way to know when something has happened is to control how often or how regularly that state of change occurs.

'clock stretching' is nothing more than change that state in an irregular fashion- in other words, keeping a state either high or low, longer that it should be, because the state has to maintained for a longer duration to indicate what state things may be in.

In i2c, because it's two-wire (aka TWI), there are only so many ways to indicate when things are working right, and or wrong, in a form of signaling communication between the master and the slave(s). Manipulation the clock is an important part of communication to the slave, or back to the master, that things are OK, or something is wrong.

I've attached an Application sheet from Texas instruments that may help you.

 

I am not using any specific device but I am reading data sheet for MCP23017

Page 14 I2C read operation.

https://ww1.microchip.com/downloads/en/devicedoc/20001952c.pdf

They seem to have put some real effort into making it confusing by using three terms for the same thing - device op code, slave address and control byte.
When you read from most I2C devices (all except the most primitive) there are multiple internal registers. First, you have to tell the device which register you want to read from. You send the register address to the device and it stores it. That’s a write operation.

when you read from the device, you read from the register that you have previously told it you want to read from.

So first, you WRITE to the device by sending the device op code Followed by the number of the address you want to read from.
Then you stop.
Then you start again with a READ command by sending the op-code and reading data. The data comes from the address you specified in the write instruction.
If you read more than one byte, the address number increments and yiu read from the next address.