We have an application board design which is under development stage and not produced yet. There are 10 to 12 chips on the board located at various locations on the 20 cm x 20 cm application board. All these chips are I2C slave chips. This application board will be attached to the microcontroller board with a board-to-board connector. The I2C master will be implemented on the microcontroller board. We need to run clock 400 kHz for all the I2C slave chips on the application board.

Question: how do I know the I2C bus competence and what should be the appropriate value for the pull up resistors ?

 

We have an application board design which is under development stage and not produced yet. There are 10 to 12 chips on the board located at various locations on the 20 cm x 20 cm application board. All these chips are I2C slave chips. This application board will be attached to the microcontroller board with a board-to-board connector. The I2C master will be implemented on the microcontroller board. We need to run clock 400 kHz for all the I2C slave chips on the application board.

Question: how do I know the I2C bus competence and what should be the appropriate value for the pull up resistors ?

https://www.nxp.com/docs/en/user-guide/UM10204.pdf

https://www.ti.com/lit/an/sbaa565/s...981&ref_url=https%3A%2F%2Fwww.google.co.th%2F

Pull up is highly dependent.....
Typically, you aim for around 3mA through the resistor
An osilloscope is highy desirable to determine what you need to meet the rising edge speeds of the specification

 

Question: how do I know the I2C bus competence and what should be the appropriate value for the pull up resistors ?

The bus capacitance is highly dependent on line width and distance of the line to the GND-layer, somewhere in the range of 0.5 - 5 pF/cm as a rule of thumb. You can measure it with an unpopulated PCB. Then you have to add the pin capacitance of each individual I2C chip. Look into their datasheets. Then you can calculate the desired pull-ups according to the I2C-spec from NXP which was mentioned by drjohnsmith.

 

As Drjohnsmith mentioned, you do require to check with a scope the I2C signals, and ensure that the rise times comfortably meet the I2C requirements, to ensure it will work and remain working across many units throughout the service life and ambient temperatures.
If you find the signals to be borderline, you may require to use an extender/active terminator like the LTC4311. I know, it IS a little pricey, but both TI and NXP have similar devices which should be more affordable.

 

Bottom line @engr_david_ee
As you see.
You can either put a lot of effort into designing and simulating the system
Or you can just put i2c buffers around
Or you can try to make it low capacitance , measure and check .

 

Bottom line @engr_david_ee
As you see.
You can either put a lot of effort into designing and simulating the system
Or you can just put i2c buffers around
Or you can try to make it low capacitance , measure and check .

Or you can run it more slowly.

 

I would add two practical things before sending the board for manufacturing.

First, check whether the microcontroller board or any of the devices already include pull-up resistors. If several pull-ups are fitted in parallel, the final resistance can become much lower than expected.

Second, make the pull-up value easy to change on the prototype. I would keep a few values such as 2.2k, 3.3k and 4.7k available, and add test points for SDA and SCL near the master and near the farthest slave.

When the first board arrives, check the rise time at the far end of the bus, not only beside the microcontroller. With a 20 cm board, 10–12 devices and a board-to-board connector, the actual waveform will probably tell you more than the trace estimate alone.

If 400 kHz is marginal, temporarily reducing the clock speed would also be a useful troubleshooting test before adding a bus buffer.