I don't understand what I'm doing wrong with ANSYS Circuit Electronics... (Bode gain using S-Parameters...)

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rdpdo

Joined Nov 2, 2020
17
Hello,

I've been trying for several days to simulate the frequency response of the circuit below using ANSYS Circuit.

First, here's what I get with LTspice:



With ANSYS, I have to use ports. For what I understand, but certainely i'm wrong, is when voltage is injected during a LNA, the voltage generator is in serie with the port impedance. If I configure them like this, here is the netlist it gives me. We see in the netlist that port2 impedance is between net PORT2 and ground, like in LTspice.



Unfortunately, this doesn't work and I get the following result:



Regarding the netlist, it should work no ?? Can someone explain me what is going wrong ??

To get the right result, I need to configure port2 with a value of 50 ohm, and referenced to itself. The resistor value need to be the same as the one in port1. For example, if I use Rport1=50, I need to set RPort2=50 to get good result.

When looking at the netlist, what I don't understand is why it only work for Rport2=50, because Rport2 is shortcuted regrading the netlist no ?? So any value for Rport2 should work no ???





I think all this is related to S-Parameters I use for tracing Gain Port2/Port1 and both port need to be same impedance to match. Is this the explanation ?

Thanks you very much for your help !
 

0ri0n

Joined Jan 7, 2025
165
You are plotting voltage gain in LTspice but transducer power gain in Ansys, that is the ratio of power delivered to the load to power available from the source. As the load is 1 GOhm, the power delivered to it will be very small which results in S21 being -87dB at frequencies close to DC. Go to results, modify the report that currently is showing you S21 and add an additional trace that shows voltage gain.

S21_&_VGIO.png

This is how adding a trace looks like in Ansoft. As Ansys bought Ansoft some time ago, it should look similar:

S21_Trace.png

VGIO_Trace.png
 
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