How to use logic circuits to reduce the pulse width?

Thread Starter

Nick Long

Joined May 12, 2020
75
Hello, my friends. Happy new year!

I want to design a logic circuit to reduce the width of a pulse waveform. The expected effect is shown in the figure below. The reduced pulse width does not need an accurate duration. It only requires a much narrower than the original width with an aligned rising edge. Of course, you can also realize this function using the non-logic circuit if you want.

Thanks.

1672819654075.png
 

ericgibbs

Joined Jan 29, 2010
18,851
Hi Nick,
I have used that CD40106 circuit on many projects, without any problems.
If you are concerned about the negative input swing, just add a diode from the input pin to 0V.
E
 

WBahn

Joined Mar 31, 2012
30,062
They're internal to the IC, together with a preceding input resistor. The clamping occurs at the distal end of that resistor.
Personally, I prefer not to rely on input protection structures as part of the normal functioning of the circuit. It would be just my luck that, down the road, someone would come out with a pin-compatible replacement that didn't have them and whoever used my design would use those parts instead. So I prefer to add clamping resistors external to the chip.

Now, if I was really pressed for board space, or for cost, I would certainly be willing to revisit this.

I also don't like injecting charge into the substrate of the IC, but that's stemming from my days as a mixed-signal IC designer of chips that were very sensitive to noise. Digital chips have pretty healthy noise immunity by their nature, so this is just me being overly cautious.
 

crutschow

Joined Mar 14, 2008
34,453
You can also add a 100kΩ resistor in series with the gate input, which will limit any negative current to a low, non-damaging value.
 

MisterBill2

Joined Jan 23, 2018
18,522
The input protection scheme in post #12 is good. To produce a narrower pulse, always the same width, use a CD4538 dual one-shot wired in the NON-RETRIGGERABLE mode. Two channels in one IC, with both positive and inverted outputs available.
 

ericgibbs

Joined Jan 29, 2010
18,851
The reduced pulse width does not need an accurate duration. It only requires a much narrower than the original width with an aligned rising edge.
Hi Bill,
If you read carefully, the TS opening post, he has not asked for the extra features you have included.
E
 

MisterBill2

Joined Jan 23, 2018
18,522
Those "extra features" do not involve extra, except for another resistor and capacitor. The dual outputs are there for free. And just like many other posts start out, we are not given much information about the application. So there might be a need for more than one pulse shrinking device required. We really have no clue.
 

Ian0

Joined Aug 7, 2020
9,822
They're internal to the IC, together with a preceding input resistor. The clamping occurs at the distal end of that resistor.
From observation, before I had SPICE, the clamping occurs at about 1V, so the SPICE model being used has no diodes. Most CMOS internal circuits are drawn in the datasheets with the diode distributed along the length of the resistor. Therefore I'd recommend a series resistor as per @crutschow , although I have used plenty of CMOS gates without, used the protection diodes to rectify AC to make the power supply, and used the output as a current limiter, all without significant failures.
 
Top