I have used serial to parallel with 74164 but i have no idea of 74595.
here is circuit page 4
http://www.nxp.com/documents/data_sheet/74HC_HCT595.pdf
here is circuit page 4
http://www.nxp.com/documents/data_sheet/74HC_HCT595.pdf
how to use 74hc595
- Thread starter RRITESH KAKKAR
- Start date
74HC595 is shift register so I say TS wants to build UART or USRT circuit for like he says serial to parallel? RRITESH KAKKAR since you already have data sheet how can we help you?And we have no idea what you are trying to do with the IC. Please explain in detail.
Last edited:
Hello,
In 74164 there was AB for data input and clk to give pulse.
in case of 74hc595 i can't guess the pin.
In 74164 there was AB for data input and clk to give pulse.
in case of 74hc595 i can't guess the pin.
Input is DS and clocks SHCP for shift register and STCP for storage register
Now I say you have datasheet so should all be there
!
OK, DS IS AB HERE CLOCK IS SHCP but how to give clock i mean storage is give different clock?
Hello,
SCK (11) for serial clock just like any other serial clock, SER (14) for serial data input,
RCK (12) to transfer parallel data to output latches, G' (13) low to enable outputs, SCLR' (10) high to NOT clear the serial registers.
The 595 is a lightly better version of the 164 in that it has separate output latches. That means when you are piping in the serial data the 8 outputs do not change right away, which allows your output states to stay the same until you get all 8 bits piped in serially. Then you can transfer the new data to the output with RCK (pin 12) when you are ready.
This would be for applications that are sensitive to the input data changing little by little instead of all at the same time. With the 164 the outputs change all the time as the serial data is being input, but with this 595 chip you can avoid that. If you are running something that already has an input clock to clock all 8 bits in at once then you dont need this chip as the 164 is adequate.
If you dont need the new functionality but dont have any 164 chips (only 595 chips) then you might get a similar functionality by tying the two clocks together, but you probably have to pipe in one extra 'do nothing' bit to get the real parallel data to transfer to the output, and keep the output pins enabled all the time. For example, if your serial stream is 11001111 (8 real bits) then you would probably have to pipe in 011001111 or 111001111 instead (9 bits) where the MSB (last bit piped in) does nothing: X11001111 (assuming you are sending LSB first).
SCK (11) for serial clock just like any other serial clock, SER (14) for serial data input,
RCK (12) to transfer parallel data to output latches, G' (13) low to enable outputs, SCLR' (10) high to NOT clear the serial registers.
The 595 is a lightly better version of the 164 in that it has separate output latches. That means when you are piping in the serial data the 8 outputs do not change right away, which allows your output states to stay the same until you get all 8 bits piped in serially. Then you can transfer the new data to the output with RCK (pin 12) when you are ready.
This would be for applications that are sensitive to the input data changing little by little instead of all at the same time. With the 164 the outputs change all the time as the serial data is being input, but with this 595 chip you can avoid that. If you are running something that already has an input clock to clock all 8 bits in at once then you dont need this chip as the 164 is adequate.
If you dont need the new functionality but dont have any 164 chips (only 595 chips) then you might get a similar functionality by tying the two clocks together, but you probably have to pipe in one extra 'do nothing' bit to get the real parallel data to transfer to the output, and keep the output pins enabled all the time. For example, if your serial stream is 11001111 (8 real bits) then you would probably have to pipe in 011001111 or 111001111 instead (9 bits) where the MSB (last bit piped in) does nothing: X11001111 (assuming you are sending LSB first).
Hello,
Not really, it's much different than the 164 chip. See post #8 above for a complete explanation.
Hello again,
Yes that's right, and i answered him. Except for one thing, the 'latch' signal is not a set logic level it is also a clock, so there are two clocks not one and he saw this that's why he asked about the 'other' clock. For another thing, it seems apparent that he already knows how to use a 164 chip.
Plus, i also explained how he could use it almost like a regular 164 chip. I dont see how this could be misinterpreted.
I'm not saying your wrong. I'm just saying I don't see why he doesn't understand how to use it. MrAI your right In all you said.
RK I bet has been told how to use these chips a 100 times I bet and every time he uses one he starts all over asking the same thing.
I wish I new where he lived I'd send him a box of note books to write down what he did last time.
You can actually overcome problem with 74hc164 like ghosting of led displays by not turning on the display till your 164 is done loaded.
RK I bet has been told how to use these chips a 100 times I bet and every time he uses one he starts all over asking the same thing.
I wish I new where he lived I'd send him a box of note books to write down what he did last time.
You can actually overcome problem with 74hc164 like ghosting of led displays by not turning on the display till your 164 is done loaded.
Last edited:
Hi,
Yes good idea with the 74xx164 chip.
Nice drawings too, i did not see them last time i was here.
Just one question, what is that 1uf cap for? Is that drawn in the right place?
I ask because normally we dont load digital lines of any kind with a direct connection to a capacitor, even a small value capacitor because for one it draws a lot of peak current from the pin and this will be repetitive if it's a clock signal. At some point I was going to suggest a small RC network to delay the latch signal so that only one uC line would be needed to drive the chip, unless he wants to stuff that extra bit i talked about in post #8.
Yes good idea with the 74xx164 chip.
Nice drawings too, i did not see them last time i was here.
Just one question, what is that 1uf cap for? Is that drawn in the right place?
I ask because normally we dont load digital lines of any kind with a direct connection to a capacitor, even a small value capacitor because for one it draws a lot of peak current from the pin and this will be repetitive if it's a clock signal. At some point I was going to suggest a small RC network to delay the latch signal so that only one uC line would be needed to drive the chip, unless he wants to stuff that extra bit i talked about in post #8.
