In my first attempt, a bipolar clock (-5V to +5V) gives a short-height square wave, which toggles between about 9.5V and 10V.
When i change clock to unipolar clock (0V to +5V) i get a steady 10V output.

My mosfet "threshold V" defaults to -1.5V in this sim, but I can change it if needed. i want typical P-channel behavior:
0V = On
5V = Off

Based on my (obviously wrong) interpretation of
https://www.electronics-tutorials.ws/transistor/tran_7.html

The middle R represent my load.

You can play with the sim here. http://tinyurl.com/y7bv7kye

A simpler attempt. Again, unipolar 5V square give flatline output.

sim: http://tinyurl.com/y7l38mo6

Thx

 

Your second circuit would work if the gate drive were to go from +10 to ground. Not sure why you put a test point at +10V, the signal would appear on the drain.

 

Your second circuit would work if the gate drive were to go from +10 to ground. Not sure why you put a test point at +10V, the signal would appear on the drain.

Thx, @DickCappels

you're right about the testpoint. P-channels are "high side", meaning they go between load and positive, correct?

You're right about clock, changing to +10V works.

But what if i want to switch a 40V load with a 5V clock? i thought switching a FET is all about the B-E differential, not to do with C?

Thx

 

That is correct. You can also use and N-Channel MOSFET as a high-side switch but it often makes the circuit more complicated, but note in the schematic below that they are using an N-Channel MOSFET as the high-side switch..

Your B-E difference translates into Gate-Source voltage, at least that's what I think you mean.

Usually the best solution to a situation like your 5 volts clock and a 40V power supply is to use a high side driver IC.

See https://www.allegromicro.com/en/Products/Motor-Driver-And-Interface-ICs/High-and-Low-Side-Drivers.aspx
for more about high-side drivers. You can also make the equivalent with discreet components if you really want to.

 

Your B-E difference translates into Gate-Source voltage, at least that's what I think you mean.

Oops, totally misspoke there. I meant gate-source.

Sounds like, to turn off a normally--on P-channel, there must be 0V differential from gate to power-supply pin, correct?

Now I finally get what drivers are for! None is needed for logic-level mosfet, correct?

A mosfet is bidirectional, so I could switch drain and source, correct?

Usually the best solution to a situation like your 5 volts clock and a 40V power supply is to use a high side driver IC.

In your linked page, does "number of bridges" mean number of drivers?

Does "high-side driver" mean for P-channel device? Or for device connected between load and plus?

They show Parallel, Direct, and SPI. I understand SPI refers to the input interface. Unclear what parallel and Direct mean .

You can also make the equivalent with discreet components if you really want to.

Could it be as simple as a single BJT or low--current FET?

THX

 

Correct: With "Normal" MOSFETs, they are off when gate voltage is equal to the source voltage. There are also depletion mode MOSFETs which are on when gate voltage is the same as source voltage, but those are rare.

If you want fast switching in a logic level MOSFET a driver is a good idea compared to the output of logic devices.

They are bidirectional but beware of the intrinsic drain to source diode..

I think "number of bridges" means the number of bridges that particular driver can support. Another way to think about it is the number of drivers.

Whether "high side driver" refers to P- channel or N-channel depends on the driver. High-side refers to a switch that connects the positive power supply to the load.

It could be a simple MOSFET or bipolar circuit.

You're welcome

 

Many thx for follow-up, @DickCappels!

"Normal" MOSFETs are off when gate voltage is equal to the source voltage.

You mean just normally-on mosfets, eg P-channel enhancement. Not all mosfets, eg not N-channel enhancement, correct?

If you want fast switching in a logic level MOSFET a driver is a good idea compared to the output of logic devices.

Even at relatively low power, like under 25W?

They are bidirectional but beware of the intrinsic drain to source diode.

So, the diode will block current from source to drain, right? Therefore, to block, we want V+ at source, gnd at drain?

It could be a simple MOSFET or bipolar circuit.

Or JFET, right?

 

jonnyradio wrote in post#7
"Normal" MOSFETs are off when gate voltage is equal to the source voltage.
You mean just normally-on mosfets, eg P-channel enhancement. Not all mosfets, eg not N-channel enhancement, correct?

N- and P-channel MOSFETs can be made as enhancement mode FETs and depletion mode FETs. I personally have never used depletion mode MOSFET but I understand they exist.

If you want fast switching in a logic level MOSFET a driver is a good idea compared to the output of logic devices. Even at relatively low power, like under 25W?

It is a trade-off, and apparently you understand it.

They are bidirectional but beware of the intrinsic drain to source diode.
So, the diode will block current from source to drain, right? Therefore, to block, we want V+ at source, gnd at drain?

The opposite - the diode is always on for voltages in excess of a diode drop when the drain and source are operated in the reverse of the typical polarity. The diode is in shunt with the drain and source.


It could be a simple MOSFET or bipolar circuit.

Or JFET, right?

Possibly, if you can find a JFET with a high enough IDss

​

 

to block, we want V+ at source, gnd at drain?

The opposite​

​

i misspoke, should have said "to open the switch", not "to block". I've seen schematics on the web showing V+ at source. From your reply, i'm guessing that means such a config is always on? And therefor only makes sense as amplifier, rather than switch?

Thx

 

Update: Sharing a solution offered on another site. Keeping in mind my question is about driving a P-channel mosfet (enhancement):

The driver needs to be two stage; an N-channel (or NPN) device that is controlled by a voltage relative to its source or emitter, in turn "pulling down" the gate of the P channel device, via and appropriate resistive divider if needed to limit the gate-source voltage on that. This is the principle, whether you use FETs or bipolar transistors.

the base-emitter junction of a bipolar transistor is effectively a diode and conducts at around 0.7V regardless of current through it. There must be a series resistor to limit the current, otherwise either the transistor or whatever feeds it will be overloaded or destroyed. The base-emitter resistors ensure a full turn-off even if there is slight leakage in other components and also speed up the turn-off time, increasing efficiency in a switching circuit. The second transistor is effectively being controlled by a switch to ground (the first transistor). The two stages are similar but mirrored between positive and negative supplies. (eg. the first stage is operated by a signal switching to a positive voltage).

Seems this gives opposite normal P behavior, which should be:

• clock low -> Q2 gate low = Q2 closed
• clock high -> Q2 gate high = Q2 open

This seems opposite, no?

1. On clock low -> Q1 base low.
2. On Q1 base low, Q1 open.
3. On Q1 open -> Q2 gate is seeing V+ (through R3.).
4. On Q2 gate = V+ -> Q2 open
5. Therefor, on clock low-> Q2 open. Not expected P-channel behavior.

1. On clock high -> Q1 base high.
2. On Q1 base high, Q1 closed.
3. On Q1 closed -> Q2 gate is seeing ground (through R2 and Q1.).
4. On Q2 gate = ground -> Q2 closed
5. Therefor, on clock high -> Q2 closed. Not expected P-channel behavior.

Thx

 

Yes, your description is correct for the BJT's.
But note that normal nomenclature is to refer to an non-conducting transistor as "off" and a conducting transistor as "on".
The description "open" and "closed" are usually reserved for relay or switch contacts.

Therefor, on clock high -> Q2 closed. Not expected P-channel behavior.

Why do you say that?
The behavior is identical for Q2 being a P-MOSFET.

When it's Vgs is zero, the P-MOSFET is off and when the Vgs has a negative voltage above the Vgs threshold voltage, as when Q1 is on, it will also be on.

 

When it's Vgs is zero, the P-MOSFET is off and when the Vgs has a negative voltage above the Vgs threshold voltage, as when Q1 is on, it will also be on.

Thx for this! I'll need to contemplate.

 

when the Vgs has a negative voltage above the Vgs threshold voltage, as when Q1 is on, it will also be on.

Q2 gate expects a negative voltage with respect to ground with a unipolar supply?

 

Q2 gate expects a negative voltage with respect to ground with a unipolar supply?

No.
It expects a negative voltage with respect to its source.
Since the P-MOSFET source is connected to V+, the its gate will be negative with respect to the source, as desired, when the gate is grounded.