Hi and a Happy New Year to all

For context, electronics are currently somewhat above my pay grade (working on it), so my flagrant use of some electronics terms does not reflect my understanding of the subject. That said, I'm ready and willing to be educated.

Attached is a section of a larger schematic but thought it best to isolate the part I am trying to 'fix'.



Q1 (a 2N3906 PNP) is acting as a high side switch for the 'load' SW1 (there is an op-amp that measures the switch resistance/voltage as it opens).

Q1 base is controlled by U1 which results in a very fast saturation and de-saturation. I would like to slow the saturation (ie when the SN7407 effectively brings Q1 base to GND) while retaining the fast de-saturation. The timing does not need to be particularly precise - approx 20us of rise time would give the op-amp time to do its thing - this could be longer but probably not shorter.

My limited understanding has of course convinced me this is possible with a capacitor/diode/resistor combination but I'm struggling to build a circuit that does it - although I can do the opposite quite easily (a small capacitor between Q1 base and GND)!

Any help or advice would be very much appreciated.

Philip

 

The problem is that you have a fast turn-on through the 7407 (which is easy to slow down), but a slow turn off through nothing but R2. To make the turn-off faster than the turn-on, you will need something that can yank the Q1 base up to 5.0 V and suck out the base charge rapidly. A standard TTL gate cannot do this because the high output voltage is only 3.5 V -ish.

An AC-series CMOS gate has an output stage that can source and sink 24 mA, which is way better than a 10 K resistor, but for real speed you need another 3906.

Schematic later.

ak

 

I would like to slow the saturation (ie when the SN7407 effectively brings Q1 base to GND) while retaining the fast de-saturation

Not totally clear.
Are you referring to the output signal rise-time, or just delaying the switching time while retaining the fast output rise-time?
My take is that you are referring to the rise-time.

 

Not totally clear.
Are you referring to the output signal rise-time, or just delaying the switching time while retaining the fast output rise-time?
My take is that you are referring to the rise-time.

Hi Zapper! - yes, you are right, it is the rise time I am trying to slow - as per the dotted line below.

 

The problem is that you have a fast turn-on through the 7407 (which is easy to slow down), but a slow turn off through nothing but R2. To make the turn-off faster than the turn-on, you will need something that can yank the Q1 base up to 5.0 V and suck out the base charge rapidly. A standard TTL gate cannot do this because the high output voltage is only 3.5 V -ish.

An AC-series CMOS gate has an output stage that can source and sink 24 mA, which is way better than a 10 K resistor, but for real speed you need another 3906.

Schematic later.

ak

Thank you ak - the turn off time is currently adequate for the requirement - only the rise time needs to be slowed. How easy would it be to do using a BJT rather than a CMOS gate? (I have plenty of 3904/6's but no CMOS's!)

 

How fast do you need the turn-off to be?

Below is the LTspice sim of the circuit modified to give a 20µs rise and a 1µs fall time (yellow trace).
It adds C1 to form a Miller integrator and slow the output rise-time.
D2 and R9 slowly discharge C1 to give a faster fall-time.
The circuit part on the left simulates a standard bipolar TTL output (red trace).

Does that do what you want?

 

An asymmetrical Miller integrator? REALLY - ?

I bow at the feet of the master.

ak

 

How fast do you need the turn-off to be?

Below is the LTspice sim of the circuit modified to give a 20µs rise and a 1µs fall time (yellow trace).
It adds C1 to form a Miller integrator and slow the output rise-time.
D2 and R9 slowly discharge C1 to give a faster fall-time.
The circuit part on the left simulates a standard bipolar TTL output (red trace).

Does that do what you want?

View attachment 311528

Oh wow! I was slightly overwhelmed by the bit on the left but then realised you were simulating the SN7407 (I think?).
If possible, I'd like to keep the turn-off to be 'vanilla' speed but the 1us delay will like not be an issue (the idea is to turn off the contacts before they fully open). I need to test this - hopefully tonight.
I forgot to mention the SN7407 is driven by a latch (SNLS02) so have both Q and _Q available via the SN7407 if needed (ie I can pull 'something' to GND when Q1 is in either state).

If I understand correctly (probably not) D2 controls the discharge of C1 while preventing Q1's base being inappropriately brought to GND and R9 controls the 'charge time' of C1?

Thank you very much.

 

Sensei Crutshow; Black belt in analog circuits.

 

I need to test this - hopefully tonight.

Well, that's disappointing... I have 22pF (plus 0.22uF, 10uF, 47nF & 100nF).
Will keep digging through my past project boxes but otherwise it's ebay wait time...

 

on the left but then realised you were simulating the SN7407

Yes, that simulates its output circuit.

D2 controls the discharge of C1 while preventing Q1's base being inappropriately brought to GND and R9 controls the 'charge time' of C1?

It's to provide an asymmetrical charge and discharge time of C1, so it slows the output rise-time as desired, but not so much the fall-time.

 

Yes, that simulates its output circuit.

Ummm ... nope.

The 7407 has an open-collector output.

I forgot to mention the SN7407 is driven by a latch (SNLS02) so have both Q and _Q available

In that case, either the Q or Q- output can drive R3 (35 K) directly.

ak

 

The 7407 has an open-collector output.

Ah, I missed that.

Below is the sim with the simulated open-collector output:
Not much change in the output.

 

Ah, I missed that.

Below is the sim with the simulated open-collector output:
Not much change in the output.

View attachment 311539

Thank you very much Zapper
I'm hoping to snag some capacitors that are nearer the correct value from a friend tonight but will be placing an ebay order too, so can I ask a couple of questions:
- R4 on my original schematic only exists because Q1's collector would be floating when the load/SW1 was open. Would R9 do the job on its own? (Hmm, just realised R( goes to both Out and GND...)
- If I wanted play with the rise time (eg reduce it), what is the relationship between C1 and R9? eg, how would I calculate their values to half the time?
- While I'm placing an ebay order, do you have any suggested useful capacitor values I should stock? I'm hoping, maybe, I'll do other similar projects.
Thank you
Philip

 

In your schematic (#1), it is R3 that keeps the Q1 collector from floating. In #13, R2 and R4 do that.

Where are you located?

ak

 

In your schematic (#1), it is R3 that keeps the Q1 collector from floating. In #13, R2 and R4 do that.

Where are you located?

ak

You are right! - I did mean to type R3 but seem to have dyslexic fingers - see also 'R(' in my previous reply which should be R9 and was too slow to notice before the edit window closed.
I'm located in UK.

 

- R4 on my original schematic only exists because Q1's collector would be floating when the load/SW1 was open. Would R9 do the job on its own? (Hmm, just realised R( goes to both Out and GND...)

Not sure, since it's not clear exactly how you are doing the measurement.

If I wanted play with the rise time (eg reduce it), what is the relationship between C1 and R9? eg, how would I calculate their values to half the time?

In my schematic, R9 is just to slowly discharge the capacitor during the OFF time of the output, it has little effect on the rise-time.
The rise-time is roughly proportional to the value of C1, so halving it value would halve the rise-time.

do you have any suggested useful capacitor values I should stock?

I would stock values from about 50pF to 1nF or thereabouts.

 

Hi and a Happy New Year to all

For context, electronics are currently somewhat above my pay grade (working on it), so my flagrant use of some electronics terms does not reflect my understanding of the subject. That said, I'm ready and willing to be educated.

Attached is a section of a larger schematic but thought it best to isolate the part I am trying to 'fix'.
View attachment 311515


Q1 (a 2N3906 PNP) is acting as a high side switch for the 'load' SW1 (there is an op-amp that measures the switch resistance/voltage as it opens).

Q1 base is controlled by U1 which results in a very fast saturation and de-saturation. I would like to slow the saturation (ie when the SN7407 effectively brings Q1 base to GND) while retaining the fast de-saturation. The timing does not need to be particularly precise - approx 20us of rise time would give the op-amp time to do its thing - this could be longer but probably not shorter.

My limited understanding has of course convinced me this is possible with a capacitor/diode/resistor combination but I'm struggling to build a circuit that does it - although I can do the opposite quite easily (a small capacitor between Q1 base and GND)!

Any help or advice would be very much appreciated.

Philip

Hello there,

I have a question for you.
Apparently the switch is closed before it is pressed which opens it.
So what is the reason for the need for the delay?

You said an op amp measures the resistance of the switch. Do you mean that you have to measure it as the voltage across it rises?
But you said you are going to measure the resistance when the switch opens.
Can you explain the need for the delay?
If the op amp is not measuring during the startup and only when the switch is pressed (to open it) then it seems strange that you would need a delay.

 

Hello there,

I have a question for you.
Apparently the switch is closed before it is pressed which opens it.
So what is the reason for the need for the delay?

You said an op amp measures the resistance of the switch. Do you mean that you have to measure it as the voltage across it rises?
But you said you are going to measure the resistance when the switch opens.
Can you explain the need for the delay?

Hi MrAl
With the normally closed switch tied to GND, the op-amp amplifies the the voltage (that will eventually be 5v when the switch is fully open) to set a LS02 latch and immediately cut power to the switch. This works fine as the switch is opened relatively slowly but once the switch is opened we have to repeatedly check to see if it has been closed in order to reset the latch. The very fast turn-on/rise of Q1 does not give the op-amp time to respond and (re)cut the power to protect the switch.
This is the initial opening of the switch:


Yellow is the voltage across the switch, blue is the op-amp output, green is the Q of the latch and pink is (probably) Q1 base.
If you compare to the image in #4, you can see (in #4) the op-amp (blue) is lagging way behind the rise of Q1 (yellow in #4) thereby allowing the voltage to rise too far before triggering the turn-off.

I hope this makes sense! It works, apart from the op-amp lag. Of course, it may also be all wrong, but I was trying to avoid that discussion for the moment...

Philip

 

Not sure, since it's not clear exactly how you are doing the measurement.
In my schematic, R9 is just to slowly discharge the capacitor during the OFF time of the output, it has little effect on the rise-time.
The rise-time is roughly proportional to the value of C1, so halving it value would halve the rise-time.
I would stock values from about 50pF to 1nF or thereabouts.

Thank you Zapper - I have ordered a selection box of 2pF to 100nF which includes the all important 220pF ones.
I have tried your schematic with a parallel array of 10(!) 22pF capacitors and haven't managed to recreate the Spice curve. There could be a number of reasons, so I will wait until I have the appropriate value single capacitor.
Philip