How to select the desired poles and zeros for compensation?

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SiCEngineer

Joined May 22, 2019
82
I have found a good document from TI on how to calculate the passive components required to design a stable compensation network/analogue feedback loop, here: http://www.ti.com/lit/an/slva662/slva662.pdf. It says in the document that "We can find the required C1, C2, C3, R2, and R3 once we select R1 with the desired fp0, fp1, fp2, fz1, and fz2 as follows." However, it gives absolutely no explanation as to how to find the desired poles and zeroes of the system? In my case I have a resonant switched mode power supply and a CLC pi filter on the output to filter ripple. How would I decide where to place the poles and zeroes without trial and error?
 

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DarthVolta

Joined Jan 27, 2015
149
I'm by no means qualified yet, but what about the fig4 on page 5 ? I've seen that general shape use

Now that I can do AC mesh and node analysis, I need to learn Bode plots and stuff, and LaPlace transforms for ODE's

What are some more details on the SMPS you have ? Whats the output current, and ripple supposed to be ? What kind of load is it for ?
 

tindel

Joined Sep 16, 2012
670
Your compensator is generally your beta (B) in your control loop. You need to know your plant or alpha (A) to determine your open loop stability, as stability is defined as A*B You can determine this through analysis of you your system or through test. This app note http://www.ti.com/lit/an/snva364a/snva364a.pdf describes one such process of testing your control loop. It's a bit of an iterative task, but can be done quickly. But if you have access to the output of the compensator then you can even measure your A directly and your B to see what you need to do to further stabilize your power supply. You generally want ~60deg of phase margin and >6dB of gain margin.
 

LvW

Joined Jun 13, 2013
878
1.) The closed-loop stability is evaluated by analyzing the loop while it is open
2.) The stability is is not "defined as A*B" - instead: A*B is the so called "loop gain" and the phase margin is found by measuring /simulating the loop gain response and finding the phase at the frequency where the magnitude crosses the 0dB line.
 
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