Hi,
I found this simple 555 timer latching circuit and and is there a way to modify this by making 4 of this and when 1 switch is turned on, pushing another button should turned it off but making this button turn on.



Thanks!

 

They are called "radio buttons". I've done them with relays...what a pain. Googled: radio button circuit

Found this: http://www.simplecircuitdiagram.com/2399-radio-buttons-using-push-on-switch-latching-circuit/

Didn't see any with 555s.

Ken

 

It could be done with 555 timers, but it's simpler using RS flip flops:


Implementing with 555 timers would require at least 4 IC's (if you used dual timers); the RS flip flop solution requires 3.

CD4043 are only guaranteed to source half a mA at VDD=5V, so take care not to load the outputs.

 

Here's a simple Radio PB circuit that uses just two CMOS chips for up to 8 push-buttons, and doesn't depend upon any timing circuits.

 

For future reference, to make more capable and compact designs. This used
Capsense to eliminate push buttons, just use pad on PCB to effect button.
This is a single chip solution, $4 board if you don't want to make your own.




Regards, Dana.

 

Dana,

The OP started out looking at 555's. I wonder if a PSoC is a bit of a stretch. A PIC would work.

Ken

 

PSOC 4, PIC, Attiny, 805X anything will do. All those parts
are 555 on steroids.

Regards, Dana.

 

Thanks for the circuits guys! I think I should now move on towards 555 chip since using micro controller or even logic ics is much better and easier.

 

From another thread. I've used variations of this circuit for many years. Only one input switch and output driver are shown. You might not need the output FET in your application. BTW, what is your application? U1 Vdd and Vss connections not shown by convention.

Note - this circuit does not have explicit exclusivity logic. However, the 574 is edge-triggered, so it should capture only the first signal in a close call. As long as one button is pressed, all others are locked out. Recovery time between buttons is about 0.2 sec. You can adjust this by changing C1.

EDIT: Wrong schematic. Wally caught it.

ak

 

I've used variations of this circuit for many years.

Really?
In that circuit all the inputs, except the PB input, follow the clock voltage through their 10k resistors, so you are depending upon the clock triggering before those inputs reach a logic one, which seems dicey.
I would not expect that to reliably happen.
A resistor, say 10k on each input to ground using another RN1 array, would prevent that from being a problem.

As long as one button is pressed, all others are locked out.

How does that occur?

 

How does that occur?

It is an edge-triggered latch. Holding a button holds the clock input high.

ak

 

OK, lets try this again. Fixed the schematic, added in the decoupling capacitor. In this version, the latch outputs go *low* when selected, so this still might not be what you are after. There is a way around that, so I'll take one more swing.

ak

 

It is an edge-triggered latch. Holding a button holds the clock input high.

Okay.
That works if the second button is pressed after the clock has already gone high.

 

There is a way around that, so I'll take one more swing.

How about adding an NPN to drive the PNP?

 

How about adding an NPN to drive the PNP?

Yeah, the sch is 1/2 modified, but I'm getting some outside work done in the sun. more later. If the output polarity is nor required to go high, then there is no reason to add the second Q.

ak

 

Last one. This one has the latch outputs going high, perfect for driving an external MOSFET for higher current drive.

If you are sure only one button will be pressed at a time, you might get away with deleting C1.

ak

 

If you are sure only one button will be pressed at a time, you might get away with deleting C1.

I agree.
With the high collector and drain resistor values, there should be enough delay in the clock signal due to stray capacitances to satisfy the D input setup time.

But my preference though would be to stay with the PNP you originally had to drive the clock, as that gives a faster clock rise-time, with less chance of a slow clock rise causing problems with the flip-flop operation.
Some edge-triggered flip-flops are sensitive to clock rise-time, although I'm not sure if this one is.

 

In sch 12, the PNP is driving the clock through a 9K - 2.2 uF time constant. In sch 16, the NPN tries to dead short a much smaller capacitor with no resistor in series, and the resulting (much faster) ramp is steepened more by the gain of the FET. You can decrease R2 for even more dv/dt.

ak